GB1569437A - Semiconductor chip interconnection - Google Patents

Semiconductor chip interconnection Download PDF

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Publication number
GB1569437A
GB1569437A GB3099477A GB3099477A GB1569437A GB 1569437 A GB1569437 A GB 1569437A GB 3099477 A GB3099477 A GB 3099477A GB 3099477 A GB3099477 A GB 3099477A GB 1569437 A GB1569437 A GB 1569437A
Authority
GB
United Kingdom
Prior art keywords
bodies
interconnection
plating
surface areas
selected surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3099477A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BAE Systems Electronics Ltd
Original Assignee
Marconi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Co Ltd filed Critical Marconi Co Ltd
Priority to GB3099477A priority Critical patent/GB1569437A/en
Publication of GB1569437A publication Critical patent/GB1569437A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/2633—Bombardment with radiation with high-energy radiation for etching, e.g. sputteretching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electroplating Methods And Accessories (AREA)

Description

(54) SEMICONDUCTOR CHIP INTERCONNECRON (71) We, THE MARCONI COMPANY LIMITED, a British Company of Marconi House, New Street, Chelmsford, Essex CMl 1PL, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: - This invention relates to a method of providing electrical interconnections for semiconductor materials. Although many methods are already in existence, a difficulty arises in providing electrical connections to certain kinds of semiconductor materials which are particularly fragile.
The present invention seeks to reduce this difficulty.
According to this invention, a method of providing an electrical interconnection between two bodies of semiconductor material includes the steps of roughening selected surface areas of each body, immersing said bodies side by side in a plating solution and illuminating with light said selected surface areas whilst the bodies are immersed until the plating deposits on the two bodies merge to form a mechanical link.
Plating occurs at the roughened areas of the body of semiconductor material and the thickness of the plating depends on the nature of the semiconductor material, the nature of the plating solution, and the time for which plating is allowed to continue.
The method is particularly suitable for use with semiconductor material which it is difficult to make electrical connections to by conventional methods such as thermo-compression bonding or soldering.
In the present method the semiconductors are not subjected to stress or shock, and if the thickness of the plating is sufficiently thick, a strong and rigid mechanical and electrical link is produced.
The invention is further described, by way of example, with reference to the drawings accompanying the Provisional specification in which Figures 1, 2 and 3 illustrate three sequential stages in the production of an interconnection between two bodies of semiconductor material.
Referring to Figure 1, there is shown therein two bodies 1 and 2 of semiconductor material. The two bodies may be composed of different materials, and each is provided with a locally roughened area 3 and 4. The roughening may be produced mechanically by abrasion or by bombardment with charged particles. The areas 3 and 4 are defined by a protective surrounding mask (not shown) to prevent damage to the region on either side. The mask is conveniently a photoresist mask, and before it is laid down the surfaces of the semiconductors should be made smooth to prevent undesired deposition of plating material at a later stage. The process may be as described in "New Semiconductor Contact Technology", Electronic Letters, Volume 12, No. 6, 18th March, 1976.
The two bodies 1 and 2 are immersed side by side in a bath of plating solution, and the mask may either be removed prior to this or left in position. The areas 3 and 4 are illuminated with light. The light from an ordinary incandescent filament bulb is sufficient. Plating proceeds in the presence of illumination in the roughened areas, and in the usual manner a progressive overhang is formed as the thickness of the plated layers 5 and 6 increases. This situation is illustrated in Figure 2. The plating process allowed to continue until the overhangs meet at the outer edges of the two bodies of semiconductor material. The two plated layers then merge and continue to grow as a single homogeneous layer, as shown in Figure 3. Growth is continued until limited by the nature of the semiconductor materials and the plating solutions or until a sufficient thickness has been built up.
Because the two semiconductor bodies are closely spaced, this method of interconnection allows a high density of interconnections to be achieved. This can be an important consideration with some kinds of semiconductor chips carrying integrated circuitry. It will be understood that overhangs are formed at each perimeter of a plated area, but only the overhangs referenced 7 and 8 in Figure 2 contribute to the interconnection.
WHAT WE CLAIM IS: - 1. A method of providing an electrical interconnection between two bodies of semiconductor material including the steps of roughening selected surface areas of each body, immersing said bodies side by side in a plating solution and illuminating with light said selected surface areas whilst the bodies are immersed until the plating deposits on the two bodies merge to form a mechanical link.
2. A method as claimed in claim 1 and wherein the selected surface areas are roughened by bombardment with charged particles.
3. A method of providing an electrical interconnection between two bodies of semiconductor material substantially as described with reference to the drawings accompanying the Provisional specification.
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (3)

**WARNING** start of CLMS field may overlap end of DESC **. materials and the plating solutions or until a sufficient thickness has been built up. Because the two semiconductor bodies are closely spaced, this method of interconnection allows a high density of interconnections to be achieved. This can be an important consideration with some kinds of semiconductor chips carrying integrated circuitry. It will be understood that overhangs are formed at each perimeter of a plated area, but only the overhangs referenced 7 and 8 in Figure 2 contribute to the interconnection. WHAT WE CLAIM IS: -
1. A method of providing an electrical interconnection between two bodies of semiconductor material including the steps of roughening selected surface areas of each body, immersing said bodies side by side in a plating solution and illuminating with light said selected surface areas whilst the bodies are immersed until the plating deposits on the two bodies merge to form a mechanical link.
2. A method as claimed in claim 1 and wherein the selected surface areas are roughened by bombardment with charged particles.
3. A method of providing an electrical interconnection between two bodies of semiconductor material substantially as described with reference to the drawings accompanying the Provisional specification.
GB3099477A 1978-05-30 1978-05-30 Semiconductor chip interconnection Expired GB1569437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB3099477A GB1569437A (en) 1978-05-30 1978-05-30 Semiconductor chip interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3099477A GB1569437A (en) 1978-05-30 1978-05-30 Semiconductor chip interconnection

Publications (1)

Publication Number Publication Date
GB1569437A true GB1569437A (en) 1980-06-18

Family

ID=10316333

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3099477A Expired GB1569437A (en) 1978-05-30 1978-05-30 Semiconductor chip interconnection

Country Status (1)

Country Link
GB (1) GB1569437A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0379616A1 (en) * 1989-01-26 1990-08-01 Siemens Aktiengesellschaft Semiconductor componant comprising superimposed semiconductor bodies

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0379616A1 (en) * 1989-01-26 1990-08-01 Siemens Aktiengesellschaft Semiconductor componant comprising superimposed semiconductor bodies

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee