GB1567500A - Data receivers - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO DATA RECEIVERS (71) We, SIEMENS AK'I'IEN GESELLSCIIAFT. a (,crm.ln Company, of Berlin and Munich, Federal Republic of Germany. do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relives to data receivers, and more pirlictilarly to a data receiver for use in a dut transmission system for receiving data words transmitted from a data transmittcr to the data receiver.

Data transmission systems are already known in which data words are transmitted by data signals from a data transmitter to a data receiver, and in which, on the occurrence of transmission errors, a given number of data words is in each case automatically repeated. Data transmission devices of this type are equipped with various checking devices for the recognition of transmission errors. For example a publication: Draeger R.J.: Oellinger M: Einkanalgeraet ARQ la fuer gesicherte Fernschreib- und Datenuebertragung. Siemens Mag. 41 (1967) pages 426 - 431 discloses a data transmission device in which a code check and an element check are carried out in the data receiver.In the code check the parity of the transmitted characters is checked and the ratio of the number of binary characters having the binary value 0 to the binary characters having the binary value 1 within a data word is checked. In the element check the distortion of the data signals is checked.

When a given distortion value is exceeded, a transmission error is indicated independently of the code check.

On the occurrence of a transmission error which is recognised as being a code error or a distortion error, an automatic repetition request is made from the data receiver to the data transmitter. For this purpose the data receiver transmits a repetition signal on a return channel, in response to which the data transmitter transmits to the data receiver a data word assigned to the repetition signal followed by a given number of the last data words to have been transmitted. Be twecn the emission of the repetition signal in the data receiver and the reception of the data word assigned to the repetition signal, no print-out of characters assigned to the data words takes place in a subscriber station connected to the data receiver.On account of the automatic repetition request, data transmission arrangements of this type are referred to as ARQ (automatic request) data transmission devices.

In a first mode of operation, the repetition of the data words is terminated when the data word assigned to the repetition signal is received in the data receiver. The termination of the repetition is effected irrespectively of whether or not all the data words have been received error-free during the repetition. In a second mode of operation the repetition is not terminated until all the data words have been received errorfree during the repetition. The first mode of operation is frequently referred to as GRQ (gated request) or "unchecked repetition process", whereas the second mode of operation is frequently referred to as TRQ 'tested request) or "checked repetition process".

On account of the automatic repetition request, the transmission link must be capable of full duplex operation, so that a data transmitter and a data receiver must be provided in each station, and the data words must be transmitted synchronously. For the connections between the data transmitters and the data receivers it is necessary to adhere to a precise pulse train which is derived from a highly constant quartz crystal oscillator in both stations. However, as it is impossible continuously to operate two in dependent oscillators, without a differcnce occurring in the phase state of the oscillations emitted therefrom, the stations are provided as a synchronising station and a synchronised station, which also makes it possible to eliminate sequences of diffcrent transit times on the transmission link.Timing pulses emitted from the synchronising station thus determine the pulse train for the entire system. The timing pulses in the receiver must therefore be brought into a phase state which is suitable for the received data signal with the aid of a synchronising device.

The lirsi operating mode has disadvantages in the bringing into phase process.

When the synchronised station is being brought into phase, the coordination between the timing pulses and the received and transmitted data signals in the synchronised station is displaced by one data elcment with each phasing step. If the synchronised station simultancously transmits specific data words, the other station can recognise incorrectly the data word which is assigned to the repetition signal. Thus the repetition process is terminated, and the next data word iS interpreted as a correct character and is emitted by the synchronising station. l'llis results in an increase in characters in the synchronising station and a character loss in the synchronised station.

Not until the synchronising station has recognised that a phase loss has occurred is the possibility of this loss of data words suppressed. The loss of a data word does not occur in the second operating mode as the probability that a complete repetition process occurs in error-free fashion is extremely low during the phasing-in. However, the second operating mode frequently is not used on account of its poorer efficiency.

This invention seeks to provide a data receiver with the aid of which the loss of data words during the phasing in process is avoided or at least reduced.

According to this invention there is provided a data receiver for use in a data transmission system for receiving data words transmitted from a data transmitter to the data receiver. comprising means for receiving the data words, a first checking device arranged to detect element or distortion errors in the received data words and upon such detection to emit a first error signal, a second checking device arranged to detect code errors in the received data words and upon such detection to emit a second error signal. which signals in the data transmission system are effective to cause the data transmitter to transmit a data word assigned to a repetition signal followed by a repeated transmission of a predetermined number of the last data words to have been transmitted, and a repetition device which is responsive to said signals and is arranged to control the reception of the data words in such manner that in a first operating mode the predetermined number of data words is repeated and in a second operating mode the predetermined number of data words is repeated until both they and the data word assigned to the repetition signal are received error-free, the repetition device comprising a logic circuit which is responsive to a further error signal (as herein defined) which indicates the occurrence of a code error during the reception of repeated data words to produce a signal which automatically establishes the second operating mode only in the presence-of a release signal (as herein defined) which indicates that the data signals are free of distortion.

Such a data receiver requires a low additional outlay and provides the advantage that no faulty characters are emitted from the data receiver during the phasing in process. Furthermore, in the transmission of coded data words, the advantage is provided that the phase for the coding is not lost. In the phasing-in process the safeguard of the second operating mode relating to the avoidance of character loss is provided without necessitating the permanent low efficiency of this second operating mode.

Preferably the repetition device comprises a bistable stage which is set during each repetition of data words and has a setting input to which the signal produced by the logic circuit is applied to maintain the bistable stage in its set state.

Advantageously the logic circuit comprises an AND gate having a first input to which the release signal is applied, a second input to which the further error signal is applied, and an output at which the signal produced by the logic circuit is produced. In this case in order to be able selectively to establish the second operating mode at any time, preferably the logic circuit further comprises an OR gate having a first input to which the release signal is applied, an output connected to the first input of the AND gate, and a second input to which a control signal is applied, the data receiver further comprising a switch which determines a first or a second binary value of the control signal thereby normally to establish selectively the first or the second operating mode.

The invention also extends to a data transmission system including a data receiver as recited above.

The invention will be further understood from the following description by way of example of an embodiment thereof with reference to the accompanying drawings, in which: Figure 1 schematically illustrates a data transmission system; Figure 2 schematically illustrates in the form of a block circuit diagram a data receiver in a data transmission station of the data transmission system; Figure 3 schematically illustrates in the form of a circuit diagram parts of the data receiver; and Figure 4 schematically illustrates as a functlon of time t signals which occur in operation of the data receiver.

Figure 1 illustrates a data transmission system comprising a synchronising data transmission station and a synchronised data transmission station, the station comprising respectively a data transmitter SS1 and SS2, a data receiver ES1 and ES2, a pulse generator TG1 and TG2, a radio transmitter FS1 and FS2, and a radio receiver FE1 and FE2. The synchronising station is connected to a punched tape transmitter LS from which data words are called up by signals emitted from the data transmitter SS1, these data words being conducted to the radio transmitter FS1 under the control of timing pulses emitted from the pulse generator 01. In the radio transmitter FS1 data signals assigned to the data words are modulated and transmitted to the radio receiver FE2 in the synchronised station, where the transmitted signals are demodulated and the data words are regained with the aid of timing pulses emitted by the pulse generator TG2. The data words are emitted from the data receiver ES2 to a page printer BS2, for example a teleprinter, which prints out characters assigned to the data words.

At the same time in a similar fashion data words emitted to a buffer store PU by a page printer BS3 provided with a key board are called up by the data transmitter SS2, transmitted from the radio transmitter FS2 to the radio receiver FE1, regained in the data receiver ES1, and printed by a page printer BS1.

In the data receivers ES1 and ES2 the data signals are checked for distortion errors in a first checking device and for parity and code errors in a second checking device.

The code check is carried out for example in that, when as is assumed here a known seven element code is used, it is checked that the ratio of the number of binary characters having the value 1 to the number of binary characters having the value 0 is always 3:4. In the event of a code error or a distortion error the relevant data receiver ES1 or ES2 emits a repetition signal which is communicated to the relevant data transmitter SS1 or SS2 respectively which consequently transmits the repetition signal as an acknowledgement and then repeats a given number of the last data words to have been transmitted, for example the last three transmitted data words.

For such automatic repetition it is necessary for the data signals to be transmitted in synchronism. To this end the pulse generators TG1 and TG2 required comprise quartz crystal oscillators, the oscillator in the pulse generator TG2 in the synchronised station being synchronised by the data signals emitted from the synchronising station. The pulse generators are brought into phase and the synchronism between the oscillators is maintained with the aid of an element-synchronisation unit and a character synchronisation unit which both act upon timing pulses emitted to the data receiver whereby an adaption to the incoming data signal and thus to the data transmitter in the opposite station is achieved.The element synchronisation unit matches the time pattern of the data receiver to the incoming data signals, and the character synchronisation unit ensures that the first element of the seven-element code data word emitted from the opposite station is treated as the first element in the data receiver.

Figure 2 illustrates in a block ES a possible form of each of the data receivers ES1 and ES2, which comprises an input circuit EG, a polarity resetting device RP, a receiver shift register ESR, a parallel-series converter PSU, the above-mentioned first checking device PW and second checking device RF, a repetition device WH, and a repetition counter WZ. Data signals from the relevant radio receiver pass via the input circuit EG and the polarity resetting device RP into the shift register ESR, and from there to the parallel-series converter PSU and thence serially to the relevant page printer BS1 or BS2.The first checking device PW compares the polarity changes of the data signals with the time pattern of timing pulses T supplied by the relevant pulse generator TG1 or TG2, and when a selected distortion value is exceeded this device PW emits an error signal SF to the repetition device WH and the data signals are evaluated as faulty. The data words present in parallel at the output of the shift register ESR are checked for the presence of incorrect combinations, for the presence of a data word assigned to the repetition signal RQ, and for the occurrence of code errors, in the second checking device RF. In the event of a code error or a parity error the device FR emits an error signal FL to the repetition device WH, and in the event of the data word assigned to the repetition signal RQ being recognised this device RF emits the signal RQ to the reptition device WH.On the occurrence of a transmission error, the repetition device WH initiates a repetition process in which time sequences are controlled by the repetition counter WZ.

Such a repetition process, in a first operating mode reference GRQ the data characters are repeated until the data word assigned to the reptition signal RQ is recognised in the data receiver ES, and transmission errors which occur during the repetition process are not taken into account. In a second operating mode referenced TRQ, the data words are repeated until they arrive fault-free in the data receiver ES. Although the operating mode TRQ has the advantage that it possesses a greater safeguard against the loss of data words, it has the disadvantage that it has a poor level of efficiency.

The loss of data words becomes particularly manifest when the data transmission stations are brought into phase and the data word which is assigned to the repetition signal RQ is recognized at random in the data receiver.

Figure 3 illustrates the repetition device WH and the repetition counter WZ in more detail, and also shows a switch SW. The repetition device WD comprises a logic circuit which consists of an OR gate D and an AND gate U, three flip-flops (bistable trigger stages) Fl to F3, two inverters Nl and N2, and a NAND gate N3. The switch SW emits a control signal ST to one input of the OR gate D, which control signal ST has the binary value 1 for the operating mode TRQ and the binary value 0 for permitting an automatic change to the operating mode GRQ. The repetition counter WZ consists of two flip-flops (bistable trigger stages) F4 and F5, a NAND gate N4, and an inverter N5.The circuit arrangement is further described below with reference to Figure 4, which shows as a function of time t the signals T. FL, SF, and RQ and further signals Sl to S4 which ococur at points indicated in Figure 3.

At a time tl, it is assumed that as a result of a distortion error, a code error is recognised in a data word. The checking devices PW and RF consequently both emit error signals SF and FL to the repetition device WH, the signal FL being applied to the flip-flops F1 and F3 and the signal SF being applied to the flip-flop F2. The output signal S3 of the flip-flop F2 and the signal ST=1 cause the automatic changes from mode TRQ (S3=1) to mode GRQ (S3=0). It is assumed that the repetition counter WZ has a count 0, so that the inverting outputs of the flip-flops F4 and F5 have the vinary value 1 (count of zero) and consequently the signal S1=0 is produced at the output of the NAND gate N4. This signal is inverted by the inverter N5.It is also assumed that the flip-flops F1 to F3 are all in the reset state so that they produce the signals S2=1, S3=1, and S4=0 respectively. At a time t2 the pulse generator emits a timing pulse T to clock pulse inputs of the flip-flops F1 to F4, as a result of which the flip-flops F1 and F2 are set, so that S2=0 and S3=0, these signals being produced at the inverting outputs of the flip-flop F1 and F2 respectively, and indicating the occurrence of the error signals FL and SF. At the same time t2 the count of the repetition counter WZ is increased by 1 to 1 so that the signal S1=1, this being the start of a repetition process.

At a time t3 on the occurrence of the next timing pulse T the next data word is received, and it is assumed that at this time no error occurs.

It is assumed that a distortion error and a code error occur in the transmission of the next data word. The flip-flop F2 remains in its set state, but now with Sl=l the flip-flop F3 is set so that S4=1 on the occurrence of a timing pulse T at a time t4. An error signal S4 at the output of the flip-flop F3 thus assumes the binary value 1 indicating the occurrence of a code error during the reception of repeated data words. Thus the error signal S4 will be referred to as a further error signal. It is assumed that the switch SW is in the solid-line position shown to permit the automatic change from the operating mode TRQ to the mode GRQ so that ST=0 and as S3=0 a signal S5 produced at the output of the AND gate U has the binary value 0.At a time t5 the data word assigned to the repetition signal RQ is recognised so that the signal RQ=1 is produced, indicating the end of a repetition process in the operating mode GRQ. At this time t5 the repetition counter WZ has reached a count of 3. With the next timing pulse T at a time t6 the repetition counter WZ again assumes the count 0 so that the signal S1=0 is again produced. The signal RQ= 1 and the output of the inverter N1 which receives the signal FL=0 at its input are conducted to inputs of the flip-flop F1 so that the time t6, with the timing pulse T, the flip-flop F1 is reset so that S2=1. The repetition process is thus terminated.With the next timing pulse T at a time t7, the flip-flop F2 is also reset, in response to the signals SF=0 and S1=0 inverted by the inverters N2 and N5 respectively, so that S3=1, and similarly the fip-flop F3 is reset so that S4=0. The sequence which takes place between the times tl and t7 corresponds to the known operating mode GRQ.

The repetition process is terminated on the occurrence of the repetition signal RQ irrespectively of whether or not a fault-free transmission of the repeated data words takes place.

At a time t8 it is assumed that a code error, but no distortion error, occurs in the mode TRQ, so that the signal FL=1 and the signal SF=0. Conseqtently, as at the time t2, the flip-flop F1 is set so that S2=0 and the reptition counter WZ assumes the count 1, since a repetition process is being commenced, so that S1=1. At a time t9 it is assumed that during the repetition process a further code error occurs, but no distortion error occurs. As at the time t4, the flip-flop F3 is set so that the further error signal S4= I.. As no distortion error has occurred, the signal S3=l is before and the mode TRO is continued.The signal S3 indicates that the data signals are free of distortion, and is conducted via the OR gate D to one input of the AND gate U, at the other input of which the signal S4= I. Therefore the signal S3 will be referred to as a release signal. (N'nsequently the signal S5=1 is produced at the output of the AND gate U, which signal S5 is fed to a setting input of the flip-flop F I and maintains the latter in its set state.

At a time I I (), as at the time t6, the repetition signal RQ is produced upon recognition of the data word assigned to this signal; in the operating mode GRO this would terminate the repetition process. As, however, the signal Fl,= I was present it the setting input of the flip-flop F3 causing the signal S4=l. the flip-fI'p Fl has remained in its set state in respect of signal S5=1 and a further repetitioll cycle is triggered in the mode TRO.It llO transmission error occurs during this kirther reptition process, the flip-flop F3 is no longer set and consequently the flip-flop Fl is no longer maintained in its set state. so that it can be reset with the next repetition signal RQ.

If only the operating mode TRQ is to be executed. the switch SW is brought into the broken-line position shown so that the control signal ST 1 is continuously produced. Consequently the AND gate U is permanently enabled. so that the signal S5 is the same as the further error signal S4, and the maintenance of the flip-flop Fl in its set state is only dependent upon whether or not the flip-flop F2 is set. Thus in this case, independently of the repetition signal RQ, each repetition process is followed by a further repetition process if any error occurs in the receipt of the data words.

WHAT WE CLAIM IS: 1. A data receiver for use in a data transmission system for receiving data words transmitted from a data transmitter to the data receiver. comprising means for receiving the data words, a first checking device arranged to detect element or distortion errors in the received data words and upon such detection to emit a first error signal, a second checking device arranged to detect code errors in the received data words and upon such detection to emit a second error signal, which signals in the data transmission system are effective to cause the data transmitter to transmit a data word assigned to a repetition signal followed by a repeated transmission of a predetermined number of the last datawords to have been transmitted, and a repetition device which is responsive to said signals and is arranged to control the reception of the dltl words in such manner that in a first operating mode the predetermined number of delta words is repeated and in a second operating mode the predetermined number of data words is repeated until both they and the data word assigned to the repetition signal are received error-free, the repetition device comprising a logic circuit which is responsive to a further error signal (as herein defined) which indicates the occurrence oí a code error during the reception ol repeillcd data words to produce a signal which automatic- ally establishes the second ()per;;itiiig mode only in the presence of a release signal (as herein defined) which indicates tli'it the data signals are free of distortion.

2. A data receiver as daimed in Claim 1 wherein the repetition device comprises a bistable stage which is set during each repetition of data words and has a setting input to which the signal produced by the logic circuit is applied to maintain the bistable stage in its set state.

3. A data receiver as claimed in Claim 1 or Claim 2 wherein the logic circuit comprises an AND gate having a first input to which the release signal is applied, a second input to which the further error signal is applied, and an output at which the signal produced by the logic circuit is produced.

4. A data receiver as claimed in Claim 3 wherein the logic circuit further comprises an OR gate having a first input to which the release signal is applied, an output connected to the first input of the AND gate, and a second input to which a control signal is applied, the data receiver further comprising a switch which determines a first or a second binary value of the control signal thereby normally to establish selectively the first or the second operating mode.

5. A data receiver substantially as herein described with reference to Figures 2 to 4 of the accompanying drawings.

6. A data transmission system including a data receiver as claimed in any of the preceding claims.

7. A data transmission system as claimed in Claim 6 and substantially as herein described with reference to Figure 1 of the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (7)

**WARNING** start of CLMS field may overlap end of DESC **. further code error occurs, but no distortion error occurs. As at the time t4, the flip-flop F3 is set so that the further error signal S4= I.. As no distortion error has occurred, the signal S3=l is before and the mode TRO is continued.The signal S3 indicates that the data signals are free of distortion, and is conducted via the OR gate D to one input of the AND gate U, at the other input of which the signal S4= I. Therefore the signal S3 will be referred to as a release signal. (N'nsequently the signal S5=1 is produced at the output of the AND gate U, which signal S5 is fed to a setting input of the flip-flop F I and maintains the latter in its set state. At a time I I (), as at the time t6, the repetition signal RQ is produced upon recognition of the data word assigned to this signal; in the operating mode GRO this would terminate the repetition process. As, however, the signal Fl,= I was present it the setting input of the flip-flop F3 causing the signal S4=l. the flip-fI'p Fl has remained in its set state in respect of signal S5=1 and a further repetitioll cycle is triggered in the mode TRO.It llO transmission error occurs during this kirther reptition process, the flip-flop F3 is no longer set and consequently the flip-flop Fl is no longer maintained in its set state. so that it can be reset with the next repetition signal RQ. If only the operating mode TRQ is to be executed. the switch SW is brought into the broken-line position shown so that the control signal ST 1 is continuously produced. Consequently the AND gate U is permanently enabled. so that the signal S5 is the same as the further error signal S4, and the maintenance of the flip-flop Fl in its set state is only dependent upon whether or not the flip-flop F2 is set. Thus in this case, independently of the repetition signal RQ, each repetition process is followed by a further repetition process if any error occurs in the receipt of the data words. WHAT WE CLAIM IS:

1. A data receiver for use in a data transmission system for receiving data words transmitted from a data transmitter to the data receiver. comprising means for receiving the data words, a first checking device arranged to detect element or distortion errors in the received data words and upon such detection to emit a first error signal, a second checking device arranged to detect code errors in the received data words and upon such detection to emit a second error signal, which signals in the data transmission system are effective to cause the data transmitter to transmit a data word assigned to a repetition signal followed by a repeated transmission of a predetermined number of the last datawords to have been transmitted, and a repetition device which is responsive to said signals and is arranged to control the reception of the dltl words in such manner that in a first operating mode the predetermined number of delta words is repeated and in a second operating mode the predetermined number of data words is repeated until both they and the data word assigned to the repetition signal are received error-free, the repetition device comprising a logic circuit which is responsive to a further error signal (as herein defined) which indicates the occurrence oí a code error during the reception ol repeillcd data words to produce a signal which automatic- ally establishes the second ()per;;itiiig mode only in the presence of a release signal (as herein defined) which indicates tli'it the data signals are free of distortion.

2. A data receiver as daimed in Claim 1 wherein the repetition device comprises a bistable stage which is set during each repetition of data words and has a setting input to which the signal produced by the logic circuit is applied to maintain the bistable stage in its set state.

3. A data receiver as claimed in Claim 1 or Claim 2 wherein the logic circuit comprises an AND gate having a first input to which the release signal is applied, a second input to which the further error signal is applied, and an output at which the signal produced by the logic circuit is produced.

4. A data receiver as claimed in Claim 3 wherein the logic circuit further comprises an OR gate having a first input to which the release signal is applied, an output connected to the first input of the AND gate, and a second input to which a control signal is applied, the data receiver further comprising a switch which determines a first or a second binary value of the control signal thereby normally to establish selectively the first or the second operating mode.

5. A data receiver substantially as herein described with reference to Figures 2 to 4 of the accompanying drawings.

6. A data transmission system including a data receiver as claimed in any of the preceding claims.

7. A data transmission system as claimed in Claim 6 and substantially as herein described with reference to Figure 1 of the accompanying drawings.