GB1566222A - Integrated circuit decoder system - Google Patents

Description

PATENT SPECIFICATION

( 11) 1 566 222 ( 21) Application No 1459/78 ( 22) Filed 16 Dec 1976 ( 62) Divided out of No 1566407 ( 31) Convention Application No 644854 ( 32) Filed 29 Dec 1975 in ( 33) United States of America (US) ( 44) Complete Specification published 30 April 1980 ( 51) INT CL 3 H 03 K 13/25 ( 52) Index at acceptance G 4 H 13 D DU ( 54) INTEGRATED CIRCUIT DECODER SYSTEM ( 71) We, MOSTEK CORPORATION, a corporation organised under the laws of the State of Delaware, United States of America and of 1215 West Crosby Road, Carrollton, Dallas County, Texas, United States of America, do hereby declare the invention for which we pray that a patent may be granted to us and the method by which it is to be performed to be particularly described in and by the

following statement:-

This invention relates generally to an integrated circuit decoder system which may be used, for example, in a random access memory most conveniently fabricated using MOSFET technology.

Large scale integrated circuits have been used increasingly in recent years for storing digital data in random access memories having both read and write capability, as well as read only capability In this type of circuit, binary address signals are applied from external control circuitry to the integrated circuit chip to identify a single binary memory cell in an array of several thousand A large number of these integrated circuit chips are typically connected in parallel in a memory system with corresponding inputs common, except for one input which provides a method of selecting only one chip In order to achieve maximum utility, the number of control signals to the chip is preferably reduced to a minimum by providing for automatic data processing within each individual integrated circuit chip For economic reasons, it is also highly desirable to provide the greatest number of binary storage cells possible on a single integrated circuit chip Attempts to increase the number of storage cells on each chip has heretofore increased the number of external connections to the chip, thus increasing the "pin count" of the package.

The combination of the increased storage capacity and greater chip area and the requirement for a package having greater pin count materially increases the cost of the circuit because of greater material cost and reduced yields.

Random access read/write memories having 4,096 storage cells arrayed in 64 rows and 64 columns have been commercially produced In order to specifically identify a single storage cell, twelve binary address signals are required, six to select a row and six to select a column.

It is generally necessary to use nine pins to input data, control operation of such a circuit, and provide power, resulting in a required total of 21 pins As a result, a 22 pin package has been used Some desirable control and power supplies have been omitted to reduce the numbers of pins to eighteen but this type circuit requires many compromises Using current semiconductor technology, a read/write random access memory having 16,384 binary storage cells on a single chip is feasible, but this increases the number of address inputs required by two.

In U K Patent Application No 50439/75 (Serial No 1,533,997) (corresponding U S.

Patent Specification No 3,969,706), a 4,096 bit random access read/write memory is disclosed and claimed which utilizes only sixteen pin package This is made possible by using the same six pins for both the row address and column address inputs to the package This is made practical by using a separate column address strobe signal to place the column select function under the control of the external central control system However, this circuit utilized separate input buffers for the row address signal and for the column address signals, and also separate row and column decode circuits disposed along adjacent edges of the memory array The number of storage cells in this circuit can be increased to 16,384 which will retain a sixteen pin package merely by using the chip select pin as the seventh address input and externally decoding either the row or column address strobe signal to provide the chip select function.

The present invention provides in an integrated circuit chip, the decoder system cn ( 19) 2 15 -2comprising, a plurality of decode nodes, a plurality of control nodes, a transfer transistors being electrically common and decode node, the gate node of the transfer transistors being electrically common an precharged to a first precharge voltage level, precharge circuit means for precharging the decode nodes to a second precharge level which is higher than one threshold below the first precharge level whereby the voltage on the gates of the transfer transistors will be capacitively boosted more than one threshold above the second precharge level to precharge the respective control nodes substantially to the second precharge level, and address circuit means for discharging all except one of the precharged decode nodes and the control nodes connected thereto to thereby capacitively reduce the voltage of the gate nodes of the transfer transistors to the first precharge voltage to turn off the transfer transistor associated with the decode node which is not discharged.

In a preferred arrangement, at least one control node is associated with each decode node An enable line is provided for each control node, and an enable line transistor connects each enable line to an enable clock signal, the gate of the enable line transistor forming a part of a respective enable line control node A charging transistor connects each enable line control node to the respective decode node, the gates of the charging transistors being electrically common and forming a common bootstrap node The precharge circuit means comprises first circuit means for charging the common bootstrap node to a predetermined first precharge level and the respective enable line control node to a predetermined second precharge level This results from capacitively boosting the common bootstrap node to more than a threshold above the predetermined second precharge voltage level, at least partially by the capacitance of the charging transistors.

Said address means comprises circuit means responsive to a plurality of binary address signals for discharging all decode nodes except one and therefore all corresponding enable line control nodes except one selected by the address signals The voltage on the common bootstrap node will thereby be reduced by the capacitive coupling to the decode nodes and the enable line control nodes will be discharged The arrangement also has means for then producing enable clock signal transitioning such that the enable line control node will be capaciitevely boosted above the second precharge level, at least partially by the gate capacitively boosted above the second transistor, to permit more rapid and more complete charging of the enable line by the enable clock signal through the enable line transistor.

Preferably, a plurality of input lines are connected to the decode circuit for a corresponding number of binary address signals The address circuit means also has an output which can be isolated from the undischarged decode nodes Control circuit means are also provided for causing the precharge and address circuit means to decode a first set of address signals, applied to the input lines, to produce a first decode signal on one of the decode nodes, and to store the decode signal produced therefrom in the respective address circuit means, and then to decode a second set of address signals applied to the input lines and produce a second decode signal on one of the decode nodes.

Said control nodes may comprise a plurality of decode signal output nodes, and rectifier means for charging the common gate node to a predetermined voltage and then holding the charge as the common gate node is capacitively boosted to a higher voltage In this case, said precharge circuit means precharges the decode nodes to a precharge voltage level for capacitely boosting the common node to a higher voltage, to turn the transistors on, and thus precharge voltage level for capacitively substantially the same precharge voltage level Also said address circuit means selectively discharges all decode nodes in response to address signals, except one decode node represented by the combination of address signals, whereby the voltage on the common node will be reduced, to turn the transistor associated with the one decode node off The corresponding output node is thereby subsequently capacitively boosted above the precharge voltage level.

The present invention also provides, in an integrated circuit chip a method of trapping a voltage on at least one of a plurality of control nodes, which method comprises, precharging each of the control nodes through a precharge node and a transistor while the gate of the transistor is more than a threshold above the voltage level of the precharge node as a result of capacitive coupling between the precharge nodes and the gates of the transistors, the gates of the transistors being electrically common, and then discharging a sufficient portion of the precharge nodes and corresponding control nodes to reduce the voltage level on the gates of the transistors interconnecting the precharge nodes and control nodes which are not discharged by said capacitive coupling to less than one threshold above the precharge voltage level to thereby trap the voltage on the control nodes not discharged.

1 566 222 1.566,222 An emodiment of the invention will now be described with reference to the accompanying drawings, wherein:Fig I is a schematic plan view of an integrated circuit chip in accordance with an embodiment of the present invention, Fig 2 is a schematic diagram of a portion of the circuit illustrated in Fig 1, Fig 3 is a schematic diagram of one of the decode circuits illustrated in Fig 2, Fig 4 is a more detailed schematic diagram of a portion of the circuit illustrated in Fig 2, Fig 5 is a timing diagram which serves to illustrate the operation of the portion of the circuit illustrated in Fig 3; Fig 6 is a schematic circuit diagram illustrating a typical storage cell from the circuit of Fig 1; and; Fig 7 is a schematic circuit diagram illustrating an input buffer of the circuit of Fig 1.

Referring now to the drawings, an integrated circuit chip in accordance with an embodiment of the present invention is indicated generally by the reference numeral 10 in Fig 1, where the dimensions of the chip 10 are shown substantially to scale in Fig 1 The circuit includes 4,096 memory cells of the type illustrated in Figure 6 Each of these memory cells includes a capacitive storage node 12 and a field effect transistor 14 which are connected between a digit line 16 and the circuit supply voltage 18, a row enable line is connected to the gate of the transistor 14 Data is stored by bringing the row enable line 20 high to turn transistor 14 on, and then bringing digit line 16 to the desired voltage, either 0 volts for a logic " O " level or some positive voltage for a logic "I" level, on storage node 12, then turning the row enable line 20 off Data is read from the storage cell by precharging line 16 to some predetermined voltage, then bringing the row enable line 20 high to turn transistor 14 on, and then sensing a voltage change on the digit line 16, the magnitude of the change being representative of whether a logic " 1 " or a logic " O " was stored in the cell For convenience, thepe cells are designated by row and colum 4 R where x is the row and y is the column For example, cells in the first row are designated RC, through R 1 Ce 4 and the cells in the first column are designated R 1 C, through R 64 C 1, although only the cells common to rows 31-34 and columns C 1-C 4 are illustrated specifically in Fig 4.

As mentioned, a total of 4,096 storage cells similar to those illustrated in Fig 6 are provided on the chip 10 If desired, 16,384 cells can also be provided One-half of the storage cells are located in the area defined by the dashed line 22 in Fig 1, and the other half in the area bounded by the dashed line 24 The storage cells in area 22 are arrayed in 32 parallel rows extending horizontally in Fig I and 64 columns extending vertically.

Similarly, the cells in array 24 are arrayed in 32 horizontal rows and 64 vertical columns.

Sixty-four amplifiers, one for each vertical column, are disposed between the two arrays of memory cells within the dotted area bounded by dashed line 26 The sense amplifiers are designated SA 1-SA 64, with enlarged portions being illustrated in Figs 2 and 4 as will presently be described An important advantage of the circuitry of Fig.

1 is that balanced dynamic sense amplifiers with split sense lines of the type described in U.K Patent Application No 52563/76, (Serial No 1,566,408) can be used This type of dynamic sense amplifier requires direct access to both halves of the selected column, and the decode method herein disclosed provides such access Thus, each of the sense amps SA,-SA,4 has true and complement digit lines, or sense _buses, which are designated C 1-C 64 and C-C 64.

although only the first sixteen pairs of the digit lines are illustrated in Fig 2.

Sixteen decoder circuits D,-D,6 are disposed in the area defined by dashed line 30, and sixteen decoder circuits D 17-D 32 are located in the area defined by dashed line 32 Six address inputs A 0-A,, which are schematically illustrated as wires ball bonded to metalized pads 34-39, respectively, are connected to six address buffers A Bo-AB, disposed substantially in the areas indicated by the corresponding dashed lines Each of the buffers AB 0-AB 5 is preferably of the sample and hold type and produce true and complement address signals.

The address input buffer AB, is illustrated by way of example in Fig 7 Address input A, is applied to terminal 31, typically as either + 0 8 volts or + 1 8 volts, representing logic levels from bipolar TTL circuitry The trap address node 33 is momentarily brought high while address node 35 is low so that transistors 37, 39 and 41 are turned on.

This results in a voltage near the voltage of address input AO being stored on nodes 43 and 45, and the reference voltage, typically + 1 4 volts, being stored on node 47 After a short period, the "trap address" node 33 goes low, and the "latch address" node 35 goes high The trapped voltages on nodes 45 and 47 are then capacitively boosted above the thresholds of transistors 49 and 51 by capacitors 53 and 55 The difference in conductance of transistors 49 and 51 due to the different voltages on nodes 45 and 47 is sensed by differential amplifier 53, the outputs of which are applied to a latch 55 which is set by the signal on the latch address input 35 This results in the 1,566,222 complementary outputs A, and A& assuming the appropriate logic levels The outputs of the latch 55 are both at low levels until occurrence of the latch clock signal as described in the above referenced U K.

Patent Application No 50439/75 (Serial No.

1,533,997.

The true and complement outputs from each of the address buffers AB 1-AB 5 are applied in various combinations to the 32 decoders D 1-D 32 as will hereafter be described in greater detail The true and complement outputs from buffer Ab, are used to select one of the two row enable outputs from each of the 32 decoders D 1D 32, as represented by lines A 1 and A O in Figure 1, and are also used to control a multiplex circuit 40 to select which pair of outputs from two read/write amplifiers 42 are connected to a data I/O bus 44 Bus 44 is connected to a data input buffer 46 and to a data output buffer 48 generally in the manner disclosed in UK Patent Application No 50439/75 (Serial No 1533997).

Four control signals designatedchijp select (CS), row addr 1 S strobe (RAS), column address strobe LCAS), and a read or write select signal WRITE are applied to inputs represented by bonding pads 50-53, respectively Data input to the data input buffer 46 is applied to pad 54, and data output from the data buffer 48 leaves on pad Four voltage supplies, including V,,, Vi, Vc C and ground, are applied to pads 56-59, respectively, thus providing a total of sixteen external connections to the chip.

In the present circuit, V,, is the maximum supply voltage and is equivalent to V, in U.K Patent Application No 50439/75 Serial No 1,533,997), and V B is more analogous to V,, in the latter application.

These external connections go to the pins of a conventional hermetically sealed in-line package Control logic, including the read/write amplifier 42, multiplex circuit 40, input buffer 46, and output buffer 48, together with internal clock generators to accomplish all necessary functions including that described in U K Patent Application No 50439/75 (Serial No.

1,533,997) is located primarily in the area defined by broken line 60 Bonding pads 50-59 are not necessarily located in the positions indicated in Fig 1, however, and are illustrated only schematically.

Each of the decoders D,-D 3, is preferably substantially as illustrated in Fig.

3, which specifically illustrates decoder D 17.

The decoder D,7 is comprised of transistors Q 1-Q 5 which are connected in parallel between a precharge node 100 and ground.

The precharge node 100 is precharged to near V,, through a transistor Q 6 in response to a precharge signal P, on line 102, which goes to VDD Precharge node 100 is connected through transistor Q 7 to the gate of a transistor Q 8, through transistor Q to the gate of transistor Q,0, and through transistor Q, to the gate of transistor Q 12.

The gates of transistors Q 8 and Q,, form row selected storage or control nodes RN 33 and RR,, respectively, and the gate of transistor Q 12 is column selected node CN.

The five sets of true and complement address signals A,-A, and A,-A, from the buffers AB 1-AB 5 are applied to lines 104113 which extend vertically through all 32 of the decoders D,-D,, The outputs A, and A, from the buffer AB, are applied to circuitry 41 which produces AO(ROW) a-nd Aj(ROW) signals during a row address cycle which are applied to thirty-two decoders D,-D 32, and signals A,(COL) and A O (COL) signals during the column address cycle which are applied to a multiplex circuit 40.

The gates of the five transistors Q,-A, of each of the decoders is connected to a unique combination of five of the ten true and complement row address lines 104113 For example, the gates of transistors Q,-Q 5 may be connected to address lines A,, A 2, A 3, A 4 and As, which is a binary representation of the number sixteen which is used in the decoder D,7 Except for the unique manner in which the gates of the transistors Q,-Q 5 of each decoder are connected to the five pairs of address lines, the remainder of the circuit illustrated within the dashed outline in Fig 3 is identical for all decoder circuits Thus the nodes 100 may conveniently be called decode nodes.

A trap row decode signal TRD, a column enable signal CE, a row enable signal REA 0, and a complement row signal RE Ao are applied to lines 114-117, respectively, which also extend through all 32 decoders.

The row enable signals REA and REA, are generated by suitable AND gates represented at 118 and 120 in response to the address signals Aj(ROW) and row enable signal RE applied to terminal 122.

Thus, either REA O or REA O is high, and the other low, in complementary fashion in response to a row enable signal RE, produced at the appropriate time during the row cycle by the timing and control circuitry.

Line 116 for the REAQ signal is connected to the drain node of transistor Q 8, and a row enable line RE 33 extends from the source node The drain node of transistor Q,, is connected to line 117 for the REA signal and the source node is connected to row enable line RE 34 The gate of transistors Q 8 and Q,, form row control nodes RN 33 and Y 534, respectively The drain of transistor Q,2 is connected to line 115, which carries the column enable signal CE, and the source is connected to column enable line CE 17.

1,566,222 The trap row decode line 114 is connected to the gates of transistors Q 7 and Q% Line 124 is connected to the gate of transistor Q, and is connected through transistor Q,3 to V,,, The other end of line 124 is normally open The gate of transistor Q,1 is also connected to V,, so as to permit node 124 to bootstrap by the stray capacitance of transistors Q,, as will hereafter be described.

There are sixty-four row enable lines RE 1-R, which extend from the thirtytwo decode circuits D,-D,, and thirty-two column enable lines CE,-CE 32 As is best illustrated in Fig 2, the row enable lines RE 1-RE 64 extend parallel along the rows of cells, although only row enable signals RE 24-RE,, from decoders D 12-D 21, respectively, are illustrated in Fig 2 It will also be understood that although only columns I-16 are illustrated, all row enable lines RE,-RE 64 extend from the decoders D 1-D 32 completely across all sixty-four columns of the array Column enable lines CE,-CE 32 also extend from the respective decoders D,-D 32 between the corresponding pairs of row enable lines extending from the same decoder The row enable lines and the column enable lines extending horizontally from the decoders D,-D 32 are typically metalized lines It will be noted, however, that each of the horizontal metalized portions of each column enable line terminates when it reaches a certain column and makes contact with a conductor at a different level in the integrated circuit, usually a diffused region or a polycrystalline semiconductor layer, and then proceeds parallel to the columns to the appropriate sense amplifier as best illustrated in Fig 2 For example, column lines CE,8 and CE,7 from decoders D,6 and D,7, respectively, transition from horizontal conductors to vertical conductors between the second and third columns and proceed downwardly and upwardly, respectively, to the row of sense amplifiers Similarly, column enable signals CE 5 and CE,1 transition between the sixth and seventh columns and proceed downwardly and upwardly, respectively, to the row of sense amplifiers Each successive pair of column enable lines emanating from decoder circuits above and below the sense amplifier row, respectively, turns and proceeds toward the sense amplifiers after every four columns so that column enable lines CE,4 and CE 19 extend vertically through the array between columns 10 and 11 and column enable line CE,3 and CE 20 extend vertically between columns 14 and 15 This is continued until finally column enable lines CE, and CE 32 proceed to the sense amplifiers between columns 62 and 63.

although this arrangement is not illustrated.

Each column enable line simultaneously enables two columns of the array as best seen in Figs 2 and 4 For example, column enable line CE,6 enables sense amps SA 1 and SA 2, while column enable line CE,7 enables sense amps SA 3 and SA 4 As previously described, two sets of true and complement data lines DL 1, DL, and DL 0.

D Lo extend along all sixty-four of the sense amps SA,-SA 64 The respective sense amps or "columns" are said to be enabled when the true and complement digit or sense lines are connected to the corresponding set of true and complement data lines For example, the split digit lines C, and C, are connected to data lines D Lo and M,0 by transistors 150 and 152, and split digit lines C 2 and C are connected to the data lines DL, and t, by transistors 154 and 156, respectively, when column enable line CE,6 is active, i e high Similarly, when column enable line CE,7 is active, transistors 158 and connect column lines C 4 and C 4 to data lines D Lo and DL 0, and transistors 162 and 164 connect column line C 3 and C 3 to data lines DL, and M 1, Thus, it will be noted that data from the cells in two adjacent columns of the selected row are connected to the respective data line pairs DL 0, E Qo and DL 1, DL 1, during each column address cycle in response to one column enable line CE,-CE 32 being active This data is sensed by the respective read/write amplifiers 42 of Fig 1, which may function in the same manner as the sense amplifiers SA, -SA 64, and the output from one of the amplifiers 42 selected by the multiplexer 40 in response to column address signals AO(COL) and A,(COL).

As mentioned, the horizontally extending row enable lines RE,-RE 64 and horizontally extending portions of the column enable lines CE,-CE 32 are typically formed by the metalized layer The digit lines C,-C 64 and C,-C 64 are normally formed by diffused regions in the semiconductor substrate The vertical portion of the column enable lines CE,CE 32 may also be formed by diffused regions connected to the metal horizontal portions of the lines by contact opening in the oxide or other insulating layers in the conventional manner Where silicon gate technology is used to fabricate the device, as in the preferred embodiment of the present invention, the digit lines C,-C 64 and C,-C 64 may be diffused regions, and the vertical portions of the column enable lines CE,-CE 32 formed by the polysilicon layer which forms the gates of transistors.

The horizontal portions of the column enable lines and the row enable lines would still be metal In either event, it is necessary to slightly spread the column lines to provide space for the vertical portions of the 1.566 222 column enable lines For this reason, it is preferable to have the column enable lines proceed from both above and below the row of sense amplifiers between the same columns in order to reduce the area which would otherwise be required.

The operation of the circuit 10 can best be understood by referring to Fig 5, which is a timing diagram of those signals relating to the addressing functions only of the circuit 10 As previously mentioned, the chip 10 can be operated by the external control circuitry exactly in the same manner as described in the above referenced U K.

Patent Application No 50439/75 (Serial No.

1,533,997), and in the commercial embodiment designed to be pin-for-pin compatible Row address signals are applied to inputs A,-A, at any time prior to a row address strobe signal RAS at terminal 51.

During this precharge period, precharge signal P, is high so that transistor Q 6 is turned on, and node 100 is precharged to VDD less one threshold since all address lines 104-113 are low During the precharge period, trap decode lines 114 is driven to VDD so that row nodes RN 33 and RN 34 are also precharged to V,, less one threshold.

Before precharge Pl goes high, column bootstrap node 124 is charged to VD O less one threshold, typically + 10 volts for VD, is equal to + 12 volts, as a result of transistor Q,3 Then when precharge signal Pl goes high, node 124 is bootstrapped to about + L 6 volts by the stray capacitance of the thirty-two transitors Q,, of the 32 decoders As a result, column node CN,7 is also charged to V, less one threshold Upon the receipt of the row address strobe signal RAS at input 51, the precharge signal P,, as represented by time line 200 falls from a high level to ground as represented by transition 200 a, and the control logic generates the series of clock pulses necessary to automatically latch input buffers ABO-AB, to produce logic signals A,-A, as represented by transition 202 a on time line 202 in Fig 5.

Since the precharge signal has gone low to turn transistor Q 6 off, and the true or complement outputs from each of the address buffers AB 0-AB, goes high, the node 100 of 31 of the 32 decoders is discharged to ground as a result of one or more of the transistors Q,-Q 5 being turned on As a result, the row nodes RN and m and the column node CN of these 31 decoders are also discharged to ground The node 100 for the selected one decoder in which all five transitors Q 1-Q 5 remains off remains high as do nodes RN and RN, and column node CN However, since column enable line CE is low, no column enable output is yet produced The trap row decode line 114, as represented by time line 204, then falls from + 12 volts to ground as represented by event 204 a, thus turning transistors Q 7 and Qq off This results intrapping a high voltage on row nodes RN and RN of the addressed decoder, and a low voltage on row nodes RN and RN of all 70 other decoders At the same time, a row enable signal on node 122 causes either the REA, or RE Ao lines 116 or 117 to go high as represented by 206 a on time line 206 of Fig 5 As a result, only one row 75 enable line goes high, with all sixty-three others remaining low, thus enabling only those cells in the one enabled row For example, if address line A, is high, and node of decoder D,7 is high, indicating that 80 decoder 17 was addressed, then row enable line RE 33 will go high and all of the other row enable lines RE 1-RE 32 and RE 34-R 64 will stay low This results in the binary data being read from cells R 33 C, through R 33 C 64 85 by the sense amps SA,-SA 64 The address lines 104-113 that were high will then return low as represented by event 202 b, typically at the same time that lines 204 and 206 make transitions 204 a and 206 a These 90 three events occur automatically a predetermined period of time after the row address strobe RAS The precharge signal also again goes high as represented by event b after events 202 b, 204 a and 206 a have 95 been completed, thus again precharging the nodes 100 of all decoder circuits D,D 32, as well as the column node CN, of all 32 decoders.

It will be noted that the bootstrap node 100 124 for the transistors Q 1,, which is represented by line 208, transitions from about + 16 volts down to about + 10 volts, as represented at event 208 a, as a result of the discharge of 31 of the 32 nodes 100 105 However, node 124 is driven back to + 16 volts, as represented by event 208 b as the 31 nodes 100 are again precharged as the transistors Q 6 are turned on at event 200 b.

Consequently, the nodes CN of all decoders 110 D,-D 32 can be fully charged to the same potential as the nodes 100, which is VDD less one threshold when the precharge signal is around VDD There are two advantages to having node 124 transition as above when 115 compared to just connecting node 124 to V,, as in the conventional manner First, during precharge, node CN more closely follows node 100 high due to a voltage above VDD on node 124 Second, after discharge of 31 of 120 32 decoders, node 124 is one threshold below VDD so that transistor Q, is off in the selected decoder so long as node 100 was precharged to two thresholds below V 00 or greater This prevents the bootstrap node 125 CN,7 from being discharged through transistor Q, on the selected decoder when the column enable line goes high and bootstraps node CN,7 above VDD.

As previously mentioned, a row address 130 7 1566222 7 strobe automatically causes one of the row enable lines RE,-RE 64 to go high and all others to remain low The control circuit logic also automatically causes each of the sense amps SA,-SA 64 to sense the logic state of the storage cell RXC, and to switch the respective digit lines C and C in accordance with the logic level sensed As a result of reading the cell, the true column line C of each sense amplifier will be at one logic level and the corresponding complement column line C will be at the other logic level.

Immediately after the input buffers AB,-AB, were latched up for the row address cycle, the signals on address inputs Ao-A, can be changed from those representing the row address of the desired cell to those representing the column address of the desired cell Then in response to a column address strobe on input 52, the precharge line 102 again transitions from high to low, as represented by event 200 c to again isolate the nodes 100 of all 32 decoders, followed by the appropriate decoder address lines 104-113 going high when the voltage on address inputs Ad-A 5 are sampled and the buffers AB,-AB, latched up, as represented by event 202 c.

This again discharges 31 of 32 nodes 100, as well as the corresponding column nodes CN However, since transistors Q 7 and Q 9 were off prior to the precharge cycle 200 b, all but one of the thiry-two row nodes RN and all but one of the thirty-two row nodes RN remain low Both the RN and the RN nodes from the previously selected row decoder remain high but only one of the two signals REA, and REAQ is high so only one row remains active The one column node CN that is held high holds the corresponding transistor Q,2 on, so that when column enable clock line 115 goes high, as represented by event 210 a on time line 210, the corresponding column enable line CE will also go high and thus become "active".

When the column enable line goes high, the true and complement column sense lines CY and C, and C,,, and C,,, of the two sense amplifiers 'addressed by the column enable line are connected to the respective pair of data lines DL O and DL O and DL, and DL,.

For example, if column enable line CE 15 goes high as a result of the column address signals, the column sense lines C, and C, are connected to data lines DL O and DL O and column sense lines C 2 and C 2 are connected to data lines DL, and DL, as a result of transistors 150, 152, 154 and 156 being turned on Since all other column enable lines remain low, no other column sense lines are connected to the data lines.

One of the two read/write amplifiers 42 of Fig _Ldetects the states of data lines DL O and DL O while the other detects the states of DL, and DL, The multiplex circuit 40 of Fig I selects the output from one of the read/write amplifiers dependent upon lines A, and A, from buffer AB, during the column address period The amplifier selected by the multiplex circuit 40 is connected to the data bus 44 which is connected to the data input buffers 46 and the data output buffer 48 As a result, the address function is the same whether reading or writing data Further, since the column address function is in response to a column address strobe, a number of storage cells in a common addressed row can be sequentially addressed without repeating the row addressing sequence.

In the preferred embodiment of the invention illustrated, a single decode node is connected to activate either of two row enable lines which are selected by one address input and each decode node is also connected to activate one column enable line which in turn enables two sense amplifiers the outputs of which are selected by one address input It will be appreciated, however, that the number of decode nodes could be doubled and one row enable line and one column enable line provided for each node, or any other convenient combination of decode nodes and row and column enable lines utilized.

An important advantage of the circuitry of Fig I is that dynamic sense amplifiers each having balanced true and complement digit lines may be used because the column address information is available on each side of each sense amplifier at the true and complement data lines This permits data to be written into either half of the memory array even though a dynamic sense amplifier is used because the sense amplifiers are not used in the write operation only the read/write amplifier 42.

Reference is made to the copending Patent Application Nos 52562/76 and 1458/78 (Serial No 1,566,407 and No.

1,566,221).

Claims (4)

WHAT WE CLAIM IS:-

1 In an integrated circuit chip, the decoder system comprising:

a plurality of decode nodes, a plurality of control nodes, a transfer transistor connecting each control node to a decode node, the gate node of the transfer transistors being electrically common and precharged to a first precharge voltage level, precharge circuit means for precharging the decode nodes to a second precharge level which is higher than one threshold below the first precharge level whereby the voltage on the gates of the transfer transistors will be capactively boosted more 1,566,222 1,566,222 than one threshold above the second precharge level to precharge the respective control nodes substantially to the second precharge level, and address circuit means for discharging all except one of the precharged decode nodes and the control nodes connected thereto to thereby capacitively reduce the voltage of the gate nodes of the transfer transistors to the first precharge voltage to turn off the transfer transistor associated with the decode node which is not discharged.

2 The decoder system of Claim I wherein at least one control node is associated with each decode node, and further comprising:

an enable line for each control node, an enable line transistor connecting each enable line to an enable clock signal, the gate of the enable line transistor forming a part of a respective enable line control node, a charging transistor connecting each enable line control node to the respective decode node, the gates of the charging transistors being electrically common and forming a common bootstrap node, said precharge ciruit means comprising first circuit means for charging the common bootstrap node to a predetermined first precharge level and the respective enable line control node to a predetermined second precharge level as a result of capacitively boosting the common bootstrap node more than a threshold above the predetermined second precharge voltage level at least partially by the capacitance of the charging transistors, said address means comprising circuit means responsive to a plurality of binary address signals for discharging all decode nodes except one and therefore all corresponding enable line control nodes except one selected by the address signals whereby the voltage on the common bootstrap node will be reduced by the capacitive coupling to-the decode nodes and enable line control nodes will be discharged, and; means for then producing enable clock signal transitioning such that the enable line control node will be capacitively boosted above the second precharge level at least partially by the gate capacitance of the respective enable line transistor to permit more rapid and more complete charging of the enable line by the enable clock signal through the enable line transistor.

3 The decoder system of Claim 1 further comprising:

a plurality of input lines to the decode circuit for a corresponding number of binary address signals, said address circuit means having an output isolatable from the undischarged decode node, and control circuit means for causing the precharge and address circuit means to decode a first set of address signals applied to the input lines to produce a first decode signal on one of the decode nodes and to store the decode signal produced therefrom in the respective address circuit means, and then to decode a second set of address signals applied to the input lines and produce a second decode signal on one of the decode nodes.

4 The decoder system of Claim I wherein said contol nodes comprise a plurality of decode signal output nodes, rectifier means for charging the common gate node to a predetermined voltage and then holding the charge as the common gate node is capactively boosted to a higher voltage, said precharge circuit means precharging the decode nodes to a precharge voltage level to capacitively boost the common node to a higher voltage to turn the transistors on and thus precharge the output nodes to substantially the same precharge voltage level, and said address circuit means selectively discharging all decode nodes in response to address signals except one decode node represented by the combination of address signals whereby the voltage on the common node will be reduced to turn the transistor associated with the one decode node off to thereby permit the corresponding output node to be subsequently capacitively boosted above the precharge voltage level.

In an integrated circuit chip, the method of trapping a voltage on at least one of a plurality of control nodes which comprises:

precharging each of the control nodes through a precharge node and a transistor while the gate of the transistor is more than a threshold above the voltage level of the precharge node as a result of capacitive coupling between the precharge nodes and the gates of the transistors, the gates of the transistors being electrically common, and then discharging a sufficient portion of the precharge nodes and corresponding control nodes to reduce the voltage level on the gates of the transistors interconnecting the precharge nodes and control nodes which 1,566,222 are not discharged by said capacitive coupling to less than one threshold above the precharge voltage level to thereby trap the voltage on the control nodes not discharged.

For the Applicants, CARPMAELS & RANSFORD, Chartered Patent Agents, 43 Bloomsbury Square, London, WCIA 2 RA.

Printed for Her Majesty's Stationery Office, by the Courier Press Leamington Spa 1980 Published by The Patent Office, 25 Southampton Buildings, London WC 2 A IAY, from which copies may be obtained.