JPH06101545B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a first-in / first-out type memory.

[Conventional technology]

The layout of the conventional read word select line drive circuit and write word select line drive circuit is shown in FIG. In FIG. 2, the entire semiconductor device has a case where it has two memory cell arrays MCA1 and MCA2 arranged in a matrix. A read word select line drive circuit RS1 and a write word select line drive circuit WS1 are arranged on both sides of the memory cell array MCA1, and similarly, a read word select line drive circuit RS2 and a write word select are also provided on both sides of the memory cell array MCA2. A line drive circuit WS2 is arranged.

The read word select line drive circuits RS1 and RS2 and the write word select line drive circuits WS1 and WS2 are respectively provided in the driver section D.
It has an R and a shift register section SR. Further, in FIG. 2, a read word select line drive clock generation circuit RCK is arranged on the lower side, and read control signals (clocks) RSG1 and RSG2 are connected to the read word select line drive circuits RS1 and RS2, respectively. There is. In addition, a write word select line drive clock generation circuit WCK is arranged on the upper side, and write control signals (clocks) WSG1 and WS
G2 is the write word select line drive circuits WS1 and WS2, respectively.
It is connected to the.

[Problems to be solved by the invention]

As described above, when the read word selection line drive circuit and the write word selection line drive circuit are arranged on both sides of each memory cell array MCA1 and MCA2, the chip size is expanded, and the read control signal and write signal are further added. However, there are inconveniences such as the circuit becoming complicated because there are many control signals.

[Means for solving problems]

A semiconductor device of the present invention has first and second memory cell arrays having read and write word select lines and bit lines arranged in a matrix, and has a function of asynchronously writing and reading. In the first-in first-out memory, the first
A read word select line drive circuit for both the first and second memory cell arrays and a write word select line drive circuit for both the first and second memory cell arrays between the first and second memory cell arrays. It is characterized by being placed in.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor device according to an embodiment of the present invention. In FIG. 1, as in FIG. 2, the entire semiconductor device has two memory cell arrays MCA1 and MCA arranged in a matrix.
The case of having CA2 is shown.

A read word select line drive circuit RS1 and a write word select line drive circuit WS1 are arranged in the center of the memory cell arrays MCA1 and MCA2. The read word selection line drive circuit RS1 and the write word selection line drive circuit WS1 have a driver section DR and a silt register section SR, respectively. Further, in FIG. 1, similarly to FIG. 2, a read word select line drive clock generation circuit RCK is arranged on the lower side, and a read control signal (clock) RSG1 is connected to the read word select line drive circuit RS1. There is. A write word select line drive clock generation circuit WCK is arranged on the upper side, and a write control signal (clock) WSG1 is connected to the write word select line drive circuit WS1.

〔The invention's effect〕

As described above, according to the present invention, since the shift register section SR can be shared by the memory cells MCA1 and MCA2, the read word selection line drive circuit RS2 and the write word selection line drive circuit WS2 are unnecessary. Therefore, the chip size can be reduced accordingly. Further, since the read control signal RSG2 and the write control signal WSG2 connected to the read word selection line drive circuit RS2 and the write word selection line drive circuit WS2 are not necessary, the circuit can be simplified.

[Brief description of drawings]

FIG. 1 shows a semiconductor device according to an embodiment of the present invention, and FIG. 2 shows a conventional semiconductor device. MCA1, MCA2 …… Memory cell array, RS1, RS2 …… Read word select line drive circuit, WS1, WS2 …… Write word select line drive circuit, RSG1, RSG2 …… Read control signal, WSG1, WSG2 …… Write Control signal for RCK ...
Read word select line drive clock generator, WCK ...
... Clock generation circuit for driving write word select line.

Claims (1)

[Claims] 1. A first-in having first and second memory cell arrays having read and write word selection lines and bit lines arranged in a matrix and having a function of asynchronously writing and reading.・ In the semiconductor device as a first-out type memory,
A read word select line drive circuit for both the first and second memory cell arrays;
And a write word select line drive circuit for both of the memory cell arrays, between the first and second memory cell arrays.