GB1565535A - Heirarchically classified multilevel storage systems and methods of operating such systems - Google Patents

Description

(54) IMPROVEMENTS IN OR RELATING TO HIERARCHICALLY CLASSIFIED MULTI-LEVEL STORAGE SYSTEMS AND METHODS OF OPERATING SUCH SYSTEMS (71) We, SIEMENS AKTIENGESELLSCH AFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to a hierarchically classified multi-level storage system and to a method of operating such a system.

In current hierarchically classified multilevel storage systems the complete programmes of individual processes running simultaneously in a data processing system which includes the storage system are stored in the lowest storage level, and each higher storage level contains only parts of these programmes. When the main store represents the lowest storage level the superordinate storage level contains only a few programme pages of a plurality of different processes, and therefore this superordinate level is referred to as the page buffer.

On account of the limited storage capacity of the page buffer, the efficiency of the storage system is particularly dependent upon the distribution of the page buffer storage space amongst the various processes. Currently, the general practice is not to transfer a store page into the page buffer until it is needed in the event of a store request. This strategy of loading the page buffer upon the occurrence of page change requests is frequently referred to as "paging on demand", and has the fundamental disadvantage of a dead time with each page transfer into the page buffer, during which time the requesting processor is unoccupied or the process in progress must be .interrupted.

In addition in data processing systems featuring multi-programme or multi-processor operation, considered from the common working store system, a plurality of processes run simultaneously for which it is necessary to provide storage capacity in the page buffer. In order to overcome the conflict which thus occurs in respect of the storage space which the various processes occupy, the fact is exploited that in a sub-sequence each process only requires a limited number of programme pages. An up-to-date storage zone, the so-called working set of a processor, is understood in this connection as the quantity of programme pages required by a process in a fixed past interval of time. Commecning with the first activation of a process, in current data processing system with virtual storage system, in programme-controlled fashion with every request for a new store page the count of a counter is increased by one, this count being reduced by one when the process releases each store page.

The situation can occur that store pages of processes in progress fill the entire page buffer.

Then on a request for a new store page a process must relase one of its own store pages, and the extent of the current storage zone does not change. On the deactivation of the process it releases all of its pages so that the corresponding page frames in the page buffer which are no longer in use are again available for the other processes.

The count of the extent of the current storage zone required in the past processing period is stored, however, in order that in the event of a reactivation the process can be provided with a number of page frames corresponding to this count. However, this does not mean that the process will still find the necessary programme pages in the page buffer, as the processes which have run in the meantime may have overwritten its programme pages as a result of their page requests. The number of times which the reactivated process must again request previously used programme pages during its processing time is dependent upon the extent to which page requests how other processes have occurred during the inactive phase of the reactivated process.

Considered over the entire length of processing, such multiple page change requests are particularly unfavourable as they each necessitate a waiting period for the requesting processor.

This invention seeks to provide a method of operation a hierarchically classified multilevel working store system by means of which the above disadvantages are reduced.

According to one aspect of the invention there is provided a method of operating a hierarchically classified, multi-level working storage system in a data processing system which simultaneously handles a plurality of processes, the two lowest levels of the storage system serving to contain all the data of the processes and comprising a main store and a page buffer, access to the buffer being obtained under the control of a store control unit wherein in the event of a store request it is established from the page address whether the request relates to a page different from that of the previous request, wherein if this is the case access is gained to page numbers which are listed in a heading of the newly requested store page and define all possible following pages to which it is possible to proceed from this store page, wherein real addresses of these following pages are formed from these page numbers by means of translation tables stored in a table store, and wherein by means of their real addresses those of these following pages which are not already present in the page buffer are selected from the main store and transferred into the page buffer.

The previously known methods or loading strategies have always been based upon the conditions which had already occurred since they are based on the "working set" in the above-defined sense. The invention, on the other hand, is based on a future "working set" and enables storage pages in the page buffer which are no longer required to be released earlier. In addition the provision of all possible following pages means that page change requests, so-called "page faults", and thus also the resultant dead times of the requesting processor are usually avoided. Thus substantially all the store requests can be handled without page change requests.

Preferably each process is divided among store pages each having a heading which indicates the page number of all possible following store pages in the process, on the loading of the storage system, for each process a page assignment table is produced in the table store in which table the page numbers of all such possible following pages are assigned real page addresses in the main storage system, adn a start address of this page assignment table in the table store is entered into an entry row of a process number table in the table store, the entry rows of which table are continuously assigned to the processes in progress by means of a process number.

Preferably on the commencement or recommencement of a process the corresponding entry row of the process number table is selected by means of the process number, and the start address of the associated page assignment table is transferred therefrom into a register of a device serving to control the provision of the following pages in the page buffer; and the page address of each newly requested store page is compared with the page address of the previously requested page, which address has been temporarily stored on the occurrence of the first store request for this store page, and in the event of nonidentity of the compared page addresses a control signal is produced which triggers the process in which the following pages are transferred into the page buffer, which process is carried out under the control of a microprocessor and the page address of the requested store page is stored in place of the previous intermediately stored page address.

Advantageously in said event of non-identity the micro-processor forms from the page address of the newly requested store page a complete address for the data words which form the heading of this store page, with this address the contents of this heading are read out from the page buffer and are entered into an intermediate store assigned to the micro-processor, and the micro-processor uses the start address and each intermediately stored page number to select an entry row in the table store to derive therefrom the real page address of each following page and uses such real page address to address the relevant store page thereby to set up this store page in the page buffer.

In another aspect the invention provides a hierarchically classified multi-level working storage system for a data processing system which simultaneously handles a plurality of processes, the two lowest levels of the storage system serving to contain all the data of the processes and comprising a main store and a page buffer, and further comprising a store control unit operable to transfer a page of data from the main store to the buffer and including means for recognising whether a store request transmitted to the apparatus relates to a different page from the previous request, a table store, control means arranged in operation in response to such recognition to read out page numbers from a heading of the newly requested page which numbers define all possible following pages to which it is possible to proceed from that store page, to derive therefrom real page addresses by reference to translation tables stored in the table store, and to transfer these real page addresses to the store control unit for transfer from the main store into the buffer of those of these following pages -which are not already present therein.

In a preferred arrangement said two lowest storage levels are composed of a plurality of storage modules each comprising a plurality of charge coupled device loops, wherein corresponding bit positions of all the loops in a module form a store page and can be synchronously displaced under the control of the store control unit, wherein each loop of each storage module includes, at corresponding bit positions forming a store page, a read/write station, and wherein the store pages formed by the read/write stations constitute the page buffer and the remaining store pages consti Xe the main store.

The store control unit preferably comprises a plurality of store control modules each assigned to a respective one of the storage modules, each store control module including a decoder which is responsive to only the Nodule address of the assigned storage module to control a store request to this storage module independently of the state of all the other store control modules. Preferably each store control module also comprises a counter register whose count represents that bit position of each loop of the assigned storage module which is present at the read/write station of the loop, a storage register which serves to store the page address in the event of a store request, a comparator which in the event of a store request serves to compare the contents of the two registers and in the event of identity to emit a ready signal which is effective to switch through to the page buffer a start signal and a word address, and means for conducting shift pulses from a pulse generator in the absence of such a ready signal and until the ready signal is produce to a counting input of the counter register and via a pulse train line to all the loops in the assigned storage module to effect said synchronous displacement of the bit positions of the loops.

The invention will be further understood from the following description by way of example of an embodiment thereof with reference to the accompanying drawings, in which:- Fig. 1 schematically illustrates a dataprocessing system with a central processor and a hierarchically classified three-level storage system; Fig. 2 schematically illustrates a storage module, constructed from charge coupled device (CCD) modules, of the storage system illustrated in Fig. 1; Fig. 3 schematically illustrates a table store which is required for the formation of real addresses of following pages; Fig. 4 shows a block circuit diagram of a store control unit of the storage system illus trated in Fig. 1; and Fig. 5 illustrates in the form of a flow diag xain the sequence in which the following pages are made available under the control of ,the store control unit of Fig. 4.

Fig. 1 illustrates a data processing system in which a central processor ZP exchanges traffic with a hierarchically classified threelevel working storage system, consisting of a high-speed buffer store or so-called "cache" CA, a page buffer store SSP, and a main store HSP. In the event of an access to the working storage system the central processor ZP first addresses the cache CA via a socalled hit/miss logic HML in which the entries in the cache are compared at least partially associatively with the hunted store address. In the event of a hit the requested store information is directly read out from the chance.

Only in the event of a miss is access given to the next lower, in this case spatially combined, storage levels, namely the page buffer store SSP and the main store HSP. These are controlled by a store control unit SST.

In this exemplary embodiment these two lowest storage levels are commonly constructed from 32 storage modules MOD1 to MOD32, one of which MODm is schematically illustrated in Fig. 2. The module MODm comprises 72 CCD sub-module SB1 to SB72 each of which comprises 256 CCD loops SL1 to SL256. It is assumed that each CCD loop has a length of 256 bits, so that if one byte comprises nine bits, i.e. eight data bits and one parity bit, the storage capacity of the module MODm is 524288 bytes and that of the entire main store HSP SSP is 16 MBytes.

Corresponding bit positions in all the CCI) loops of the module MODm form a store page, which consequently has a storage capacity of 2 kBytes. For example corresponding bit positions forming a store page SLPn are indicated in Fig. 2. At other corresponding bit positions forming a store page Sm shown by broken lines in Fig. 2 each CCI) loop contains a read/write station L/S. This store page Sm forms one of 32 store pages S1 to S32 (i.e. one in each module MOD1 to MOD32 see Fig. 1) which constitutes the page buffer SSP; the other 255 store pages in each module MOD constitutes the main store HSP. Thus although the main store HSP and the page buffer SSP are spatially combined in one unit they are nevertheless classified into two hierarchy levels, the page buffer SSP having the higher level. The basic construction of CCD loops as described above is known for example from "The Journal of Vacuum Science and Technology", Volume 9, No. 4 July/August 1972, pages 1166 to 1181.

In the combined main store HSP and page buffer SSP so-called cross-addressing is used.

All the CCD loops of each storage module are synchronously displaced, so that all the words of a store page are simulatneously present at the read/write stations L/S of each module.

Following this synchronous shift all the words of a store page Sm are stored in the read/write Stations L/S, to which end these stations must be designed with storage properties and a start/stop operation must be possible in the CCD loops. This requirement can be achieved for example with appropriately modified MOS technology.

With this structure the main store HSP and the page buffer SSP form a structural unit with an internal interface which in each storage module MOD has a data width of one store page, i.e. the words of a store page are transmitted in parallel. This is carried out at a high data rate as only a simple shift process, and not a shift and read-out process, is necessary. As a further chracteristic of this store structure, the information contained in the page buffer SSp is stored in non-redundant fashion, i.e. the main store HSP does not also contain this information.

In an alternative store structure which may be used if only a relatively small data width of the interface between the page buffer SSP and the main store HSP is required, the store page Sm can be transmitted in serial fashion into the page buffer SSP and the information in the CCI) loops of the main store HSP can be stored in serial fashion. In this case consecutive data words of a store page lie at consecutive storage positions of the CCD loops of a loop group which for example comprises all the first CCD loops SL1 of the storage modules SUB 1 to SB72. In this case the size of the page will be selcted to be such that in the case of a page transmission one cyle through all parallel operating loops, i.e. one loop group over all the store positions, is necessary. With such a store structure one usually refers to series addressing.

The page buffer SSP can also be assigned an overflow buffer, which is not shown in Fig. 1 because it is not externally recognisable but forms a hierarchy level together with the page buffer SSP, rather than a separate level. It takes from the page buffer SSP displaced store pages, if these are to be further used. It is thus possible to avoid multiple page change requests, so-called multiple "page faults", which otherwise occur in the event of requests for several processes to the same storage module with a constant resetting of the currently requested store page in the page buffer SSP. The hierarchy level formed by the page buffer SSP and the overflow buffer can therefore contain more than one store page for each storage module. Store accesses to this hierarchy level are then selectively controlled for the page buffer or the overflow buffer by the store control unit SST.

In this multi-level storage system the complete programmes, with the exception of the pages stored in the page buffer SSP, are contained in the lowest hierarchy stage, i.e. in the main store HSP. The page buffer SSP alsways contains a few programme pages of a plurality of different programmes which are simultaneously processed by the processor ZP schematically illustrated in Fig. 1. The indication of a single processor here is merely by way of example of the mode of operation of the storage system and does not represent a limitation on its fundamental operating characteristics, so that the following explanations can equally be applied to multiprocessor systems.

As is known the function of multi-level storage systems having a large storage capacity is to keep available those items of information to which, with a certain probability, access will soon be gained, in such manner that they can be acquired in as short a time as possible. The so-called loading strategy, i.e. the distribution of the items of information among the individual hierarchy stages of the storage system, therefore fundamentally determines the efficiency of the storage system.

The application of a conventional loading strategy for the page buffer SSP would be as follows. If, in a store access, a miss occurs in the cache CA, access is gained to the page buffer SSP. If it is established that the requested store page is not present therein, this page is subsequently searched for in the main store HSP. This process has the basic disadvantage of a dead time up to the end of the requisite page transfer into the page buffer SSP from the main store HSP, during which time the requesting processor is idle or the programme in progress must be interrupted.

In order to reduce such page change requests during a programme sequence (socalled "page faults"), loading strategies consisting of pre-loading or pre-setting in the page buffer SSP are employed a loading strategy of this type will now be explained in the following.

In the data processing system schematically illustrated in Fig. 1, various processes are handled simultaneously, i.e. parts of different programmes are run through consecutively.

As is known, during the running of a prog- ramme it is not necessary for the entire programme to be constantly kept available in a high hierarchy level of the storage system, as has been proved by theoretical investigations.

Such investigations carried out on programmes in very different fields of use have in fact proved that the active zone of a programme, the so-called "working set", is of different sizes and generally comprises between 5 and about 35 store pages, this upper limit being reached only rarely and being exceeded in exceptional cases.

To avoid multiple and even simple pagechange requests, those store pages which will shortly be required are prepared in the page buffer. This quantity of store pages which will shortly be required comprises all the data zones and programme pages into which the programme could jump from the store page currently being processed. This set of follow ing pages is determined at the time of the translation of a programme, and is entered into a heading at the start of each store page.

For this purpose it is necessary for the translation programme of the data-processing system, the so-called "compiler" which translates programmes out of the source Ianguage e.g. "FORTRAN" into the computer language, to divide the programme into store pages and to analyse all the programme statements in such manner that the overshooting of pages is noted in a store zone at the beginning of every store page by the indication of the page nembers SNm of the following pages in question. Because at the time of the translation of a programme the storage Iocations in the main store HSP are unknown, when a programme is loaded a page assignment table SZT is produced. In this table the page numbers SNm formed by the translation programme are assigned real main store page addresses MA, SP. This page assignment table SZT is entered into a table store TSP such as is schematically illustrated in Fig. 3. For each process PRi there is provided a page assignment table SZTi, which is assigned to the process by means of a process number i carried by the data processing system. Therefore in the table store TSP the process number i can be used to find the correct page assignment table SZTi. The table itselfisprogressively builtupin accordancewith the page numbers produced by the translation programme with which number it is also possible to address the entries in the table itself. Overall the contents of the main store HSP are described by all the page assignment tables SZT.

The page assignment tables SZT are addressed as follows: The sub-store TSP contains another table, a so-called process number table PNT, whose entry rows, classified in accordance with process numbers PRi, each contains the start address ASZT of the page assignment table SZTi of the process PRi. The start address APNT which is required for the access to this process number table PNT in the table store TSP is available as a base address in a working register.

Thus in a first step, the process number table PNT contained at a fixed position in the table store TSP can be addressed and the start address ASZT of the associated page assignment table SZRi can be taken from the entry row assigned to the relevant process PRi. At the beginning of the processing phase of each process, this start address ASZT of the associated page assignment table SZT is taken from the process number table PNT.

This address is then constant until a new process change and until then is contained in a reserved working register of the store control unit SST. Thus a process runs until one of the store accesses involves moving to a new page. This criterion is then the impetus for the store control unit SST to set up the possible pages following this new page.

This process will now be explained making reference to the store control unit SST represented as a block circuit diagram in Fig. 4 and to the flow diagram shown in Fig. 5. The store control unit SST includes a 24 bit address register AR the contents of which serve to address the CCI) store (the main store HSP and the page buffer SSP) in the event of a store request. The first five bits 0 to 4 form a module address MA which serves to select one of the 32 modules MOD. The next eight bit positions 5 to 12 define corresponding bit positions in all the CCI) loops, and hence form a store page address SP. The remaining 11 bit positions 13 to 23 form a word address WA of a data word within the store page addressed in this way. In the event of a store request the address is fed via groups of lines (which in Fig. 4 are more heavily emphasised) in parallel to 32 store control modules ST1 to ST32 which are assigned each to a respective one of the storage modules MOD1 to MOD32 of the CCI) store. These store control modules STI to ST32 are likewise fed in parallel by a control line ST which supplies a start signal for a read or write process in the page buffer SSP.

The store control unit SST also contains a device for setting up the following pages.

This device basically consists of a microprocessor MP which is assigned the table store TSP referred to above, a microprogramme store MSP, and an intermediate store ZSP. Also connected to the microprocessor MP is a working register A-REG which contains the start address ASZT, which has been determined in the manner described above, of the page assignment table SZT associated with the process in progress. Also provided is a further working register B-REG which, prior to a new page request, contains the complete page address MAl, SP1 of the last store page whose following pages have been set up. The full page address MA, SP of the newly requested store page is entered into a third working register C-REG. The contents of the registers B REG and C-REG are compared in a comparator VG1. As soon as the register contents differ, i.e. in the event of a page change, the micro-processor MP is started (first step in Fig. 5) by an output signal from the comparator VG1, which output signal is inverted by an inverter J, in order to address the heading of the newly requested store page and the abovedescribed tables. At the same time the complete page address MA, SP of the newly requested store page is transferred from the address register AR as a new comparison address MA1, SPA 1, via two gate circuits which are schematically illustrated as AND gates UGl and UG2, into the second working register B-REG. For this purpose the two AND gates UGI and UGZ are enabled by the inverted output signal of the comparator VGI.

The sequence controlled by the microprogramme of the micro-processor MP is now as follows: The micro-processor MP addresses a store page in the page buffer SSP with the page address MAl, SP1 contained in the working register B-REG (i.e. the newly requested page, which is already available in the buffer by virtue of a previous "setting-up" operation), and causes the data words contained in its heading and having (it is assumed the word addresses WA to WAk to be transferred into the intermediate store ZSP (second step in figure 5). The micro-processor MP then takes from this heading in the intermediae store ZSP the first entry, which is obtained with the word address WAID and constitutes one of the "following page" numbers SN produced by the translation programme, and with this and the start address ASZT contained in the working register A-REG addresses the table store TSP to read out from the relevant page assignment table SZT the complete page address MA', SP' of the following page in question (third to fifth steps in figure 5). This address is conducted via a multiplexer MUX to the address lines leading to the store control modules ST1 to ST32 (sixth step in figure 5).

The module address MA' selects a control module and in a manner which will be explained below automatically assumes the control of the setting-up of the requested store page. Whilst this is effected the above process is carried out for the next following page to be set up (interrogation step and return loop in figure 5). As the time until the setting up of the store page in the page buffer SSP corresponds on average to the duration of half a loop cycle, whereas the determination of a following page to be set up always only necessitates a few micro-programme steps and one access to the table store TSP, it can be assumed that the following page is in progress virtually simultaneously in all the storage modules MOD, i.e. stricktly speaking the storage modules are started very rapidly one after another With every such request of the microprocessor MP to set up a following page, by means of the module address MA' switched through via the multiplexer MUX one of the store control modules ST1 to ST32 is selected.

To this end each store control module includes a decoder DEC which when the relevant module is addressed enables an AND gate UG3 to switch through the page address SP' to a sotrage register SPR. After the transfer of this page address into the storage register SPR, the latter emits an acknowledgement signal Q which is received by the microprocessor MP from which the address of the next following page can be emitted.

If the store page designated by the page address SP is already contained in the pag the setting up of the following pages. This programme-dependent exceptional case, resulting in a dead time for the requesting processor, does however occur with the conventional loading strategies with all page change requests.

It is also conceivable that very long data sections extending over a pluality of store pages will occur in one process. In this case, since the jump-in point of the process can be any one of the section elements, it would be necessary to preset the entire section. In this case it will be more expedient to set up a store page which is then required only on request rather than preselecting a large number of following pages.

Apart from the above exceptions, the deliberate pre-loading of future required store pages into the page buffer generally avoids dead times of the requesting processors in multi-processor operation and during running processes in multi-programme operation. In addition the occurrence of the two exceptions can be further limited if a high-speed data transmission can be ensured via the internal interface of the page buffer SSP to the main store HSP, for which purpose the described "cross-addressing" store structure is itself advantageous.

WHAT WE CLAIM IS: 1. A method of operating a hierarchically classified, multi-level working storage system in a data processing system which simultaneously handles a plurality of processes, the two lowest levels of the storage system serving to contain all the data of the processes and comprising a main store and a page buffer, access to the buffer being obtained under the control of a store control unit, wherein in the event of a store request it is established from the page address whether the request relates to a page different from that of the previous request, wherein if this is the case access is gained to page numbers which are listed in a heading of the newly requested store page and define all possible following pages to which it is possible to proceed from this store page, wherein real addresses of these following pages are formed from these page numbers by means of translation tables stored in a table store, and wherein by means of their real addresses those of these following pages which are not already present in the page buffer are selected from the main store and transferred into the page buffer.

2. A method as claimed in Claim 1, wherein each process is divided among store pages each having a heading which indicates the page numbers of all possible following store pages in the process, wherein on the loading of the storage system, for each process a page assignment table is produced in the table store in which table the page numbers of all such possible following pages are assigned real page addresses in the main storage system, and wherein a start address of this page assignment table in the table store is entered into an entry row of a process number table in the table store, the entry rows of which table are continuously assigned to the processes in progress by means of a process number.

3. A method as claimed in Claim 2, wherein on the commencement or recommencement of a process the corresponding entry row of the process number table is selected by means of the process number, and the start address of the associated page assignment table is transferred therefrom into a register of a device serving to control the provision of the following pages in the page buffer, wherein the page address of each newly requested store page is compared with the address of the previously requested page which address has been temporarily stored on the occurrence of the first store request for this store page, and wherein in the event of non-identity of the compared page addresses a control signal is produced which triggers the process by which the following pages are transferred into the page buffer, which process is carried out under the control of a micro-processor and the page address of the requested store page is stored in place of the previous intermediately stored page address.

4. A method as claimed in Claim 3 wherein in said event of non-identity the microprocessor forms from the page address of the newly requested store page a complete address for the data words which form the heading of this store page, wherein with this address the contents of this heading are read out from the page buffer and are entered into an intermediate store assigned to the microprocessor, and wherein the micro-processor uses the start address and each intermediately stored page number to select an entry row in the table store to derive therefrom the real page address of each following page and uses each such real page address to address the relevant store page thereby to st up this store page in the page buffer.

5. A method of operating a hierarchically classified multi-level storage system substantially as herein described with reference to the accompanying drawings.

6. A hierarchically classified multi-level working storage system for a data processing system which simultaneously handles a plurality of processes, the two lowest levels of the storage system serving to contain all the data of the processes and comprising a main store and a page buffer, and further comprising a store control unit operable to transfer a page of data from the main store to the buffer and including means for recognising whether a store request transmitted to the apparatus relates to a different page from the previous request3 a table store, control means

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (11)

**WARNING** start of CLMS field may overlap end of DESC **. the setting up of the following pages. This programme-dependent exceptional case, resulting in a dead time for the requesting processor, does however occur with the conventional loading strategies with all page change requests. It is also conceivable that very long data sections extending over a pluality of store pages will occur in one process. In this case, since the jump-in point of the process can be any one of the section elements, it would be necessary to preset the entire section. In this case it will be more expedient to set up a store page which is then required only on request rather than preselecting a large number of following pages. Apart from the above exceptions, the deliberate pre-loading of future required store pages into the page buffer generally avoids dead times of the requesting processors in multi-processor operation and during running processes in multi-programme operation. In addition the occurrence of the two exceptions can be further limited if a high-speed data transmission can be ensured via the internal interface of the page buffer SSP to the main store HSP, for which purpose the described "cross-addressing" store structure is itself advantageous. WHAT WE CLAIM IS:

1. A method of operating a hierarchically classified, multi-level working storage system in a data processing system which simultaneously handles a plurality of processes, the two lowest levels of the storage system serving to contain all the data of the processes and comprising a main store and a page buffer, access to the buffer being obtained under the control of a store control unit, wherein in the event of a store request it is established from the page address whether the request relates to a page different from that of the previous request, wherein if this is the case access is gained to page numbers which are listed in a heading of the newly requested store page and define all possible following pages to which it is possible to proceed from this store page, wherein real addresses of these following pages are formed from these page numbers by means of translation tables stored in a table store, and wherein by means of their real addresses those of these following pages which are not already present in the page buffer are selected from the main store and transferred into the page buffer.

2. A method as claimed in Claim 1, wherein each process is divided among store pages each having a heading which indicates the page numbers of all possible following store pages in the process, wherein on the loading of the storage system, for each process a page assignment table is produced in the table store in which table the page numbers of all such possible following pages are assigned real page addresses in the main storage system, and wherein a start address of this page assignment table in the table store is entered into an entry row of a process number table in the table store, the entry rows of which table are continuously assigned to the processes in progress by means of a process number.

3. A method as claimed in Claim 2, wherein on the commencement or recommencement of a process the corresponding entry row of the process number table is selected by means of the process number, and the start address of the associated page assignment table is transferred therefrom into a register of a device serving to control the provision of the following pages in the page buffer, wherein the page address of each newly requested store page is compared with the address of the previously requested page which address has been temporarily stored on the occurrence of the first store request for this store page, and wherein in the event of non-identity of the compared page addresses a control signal is produced which triggers the process by which the following pages are transferred into the page buffer, which process is carried out under the control of a micro-processor and the page address of the requested store page is stored in place of the previous intermediately stored page address.

4. A method as claimed in Claim 3 wherein in said event of non-identity the microprocessor forms from the page address of the newly requested store page a complete address for the data words which form the heading of this store page, wherein with this address the contents of this heading are read out from the page buffer and are entered into an intermediate store assigned to the microprocessor, and wherein the micro-processor uses the start address and each intermediately stored page number to select an entry row in the table store to derive therefrom the real page address of each following page and uses each such real page address to address the relevant store page thereby to st up this store page in the page buffer.

5. A method of operating a hierarchically classified multi-level storage system substantially as herein described with reference to the accompanying drawings.

6. A hierarchically classified multi-level working storage system for a data processing system which simultaneously handles a plurality of processes, the two lowest levels of the storage system serving to contain all the data of the processes and comprising a main store and a page buffer, and further comprising a store control unit operable to transfer a page of data from the main store to the buffer and including means for recognising whether a store request transmitted to the apparatus relates to a different page from the previous request3 a table store, control means

arranged in operation in response to such recognition to read out page numbers from a heading of the newly requested page which numbers define all possible following pages to which it is possible to proceed from that store page, to derive therefrom real page addresses by reference to translation tables stored in the table store, and to transfer these real page addresses to the store control unit for transfer from the main store into the buffer of those of these following pages which are not already present therein.

7. A storage system as claimed in claim 6, in which said two lowest storage levels are composed of a plurality of storage modules each comprising a plurality of charge coupled device loops, wherein corresponding bit positions of all the loops in a module form a store page and can be synchronously displaced under the control of the store control unit, wherein each loop of each storage module includes, at corresponding bit positions forming a store page, a read/write station, and wherein the store pages formed by the read/write stations constitute the page buffer and the remaining store pages constitute the main store.

8. A system as claimed in claim 7, wherein the store control unit comprises a plurality of store control modules each assigned to a respective one of the storage modules and wherein each store control module includes a decoder which is responsive to only the module address of the assigned storage module to control a store request to this storage module independently of the state of all the other store control modules.

9. A system as claimed in Claim 8 wherein each store control module of the store control unit also comprises a counter register whose count represents that bit position of each loop of the assigned storage module which is present at the read/write station of the loop, a storage register which serves to store the page address in the event of a store request, a comparator which in the event of a store request serves to compare the contents of the two registers and in the event of identity to emit a ready signal which is effective to switch through to the page buffer a start signal and a word address and means for conducting shift pulses from a pulse generator, in the absence of such a ready signal and until the ready signal is produced, to a counting input of the counter register and via a pulse train line to all the loops in the assigned storage module to effect said synchronous displacement of the bit positions of the loops.

10. A system as claimed in any of Claims 6 to 9 for operation in accordance with the method of Claim 4, and wherein the store control unit comprises a device which serves to control the provision of the following pages in the page buffer, which device comprises a micro-processor which has output lines which can be switched through to address lines leading to the store control moduIes, a micro-programme store assigned to the micro-processor, an intermediate store for storage of the heading of a newly requested store page, a register for the start address, a second register which serves for said temporary storage of the page address, a third register which serves to store the page address of a newly requested store page, a comparator having inputs connected to outputs of the second and third registers and serving to compare the register contents and having an output of which is arranged to produce a comparison result signal, and means for triggering the micro-processor and for entering the page address of the newly requested store page into the second register in the event that the comparison result signal indicates non-identity of the compared register contents.

11. A hierarchically classified multi-level storage system substantially as herein described with reference to the accompanying drawings.