GB1558957A

GB1558957A - Isolating semiconductor devices

Info

Publication number: GB1558957A
Application number: GB1411378A
Authority: GB
Inventors: Tony Charles Denton
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1978-04-11
Filing date: 1978-04-11
Publication date: 1980-01-09

Description

(54) ISOLATING SEMICONDUCTOR DEVICES (71) We, STANDARD TELE PHONES AND CABLES LIMITED, a British Company of 190 Strand, London W. C. 2, England, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to semiconductor isolation techniques and to semiconductor structures fabricating thereby, and in particular to an isolation technique for a monolithic linear amplifier.

Accorciin-t------ An embodiment of the invention will now be described with reference to the accompanying drawing which is a schematic view of a semiconductor device provided with dielec- tric isolation.

Referring to the drawing, an n +type silicon substrate 11 is provided with an n-type epitaxial layer 12. A well 13 is etched into the substrate from the underside and in a region in register with a region 20 of the epitaxial layer 12 in which a circuit is to be formed, the well extending through the substr ; it- t- 3 r"-'

ERRATUM SPECIFICATION NO 1558957 Page 52 below heading (52) Index at Acceptance insert (72) Inventor TONY CESARIWES DENTON Bas 757171' page 1, below headi g () THE PATENT OFFICE 1 April 1980 . 01,) IdLC saici . c, lon trom the epitaxial layer and the substrate.

According to another aspect of the inven- tion there is provided a semiconductor structurc, including a semiconductor substrate on a major surface of which an epitaxial layer is disposed, a semiconductor device formed in a region of the epitaxial layer, a well provided in said substrate extending from a surface opposite said one surface substantially to the epitaxial layer and in register with the region, and an annulus of oxidised semiconductor material surrounding said region and extending through the epitaxial layer into said well, the annulus isolating the region from the epitaxial layer and the substrate. uy uY m uxiae above the surface can be reduced by first etching a moat in the region where the oxidation is to be performed. As a typical semiconductor device is less than 100 microns square, the oxide region 15 has sufficient strength to support the isolated region 20 of the silicon wafer 12.

The isolation technique is applicable primarily to the fabrication of a monolithic amplifier structure in which the isolated region contains the input transistor of the amplifier, the driver and output stages of the amplifier being formed in adjacent nonisolated regions of the epitaxial layer and coupled to the input transistor via metallised connections.

The transistor comprising the stages of the (54) ISOLATING SEMICONDUCTOR DEVICES (71) We, STANDARD TELE PHONES AND CABLES LIMITED, a British Company of 190 Strand, London W. C. 2, England, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to semiconductor isolation techniques and to semiconductor structures fabricating thereby, and in particular to an isolation technique for a monolithic linear amplifier.

According to one aspect of the invention there is provided a method of isolating a semiconductor device formed in a region of an epitaxial semiconductor layer disposed on a major surface of a semiconductor substrate, the method including etching a well into the substrate from a surface opposite the major surface, said well being in register with the region and extending substantially tQ the epitaxial layer, masking the surface of'the epitaxial layer so as to leave an annulus of exposed semiconductor material surrounding said region, and subjecting the masked surface to an oxidation process so as to grow a ring of oxide through the epitaxial layer and into the A, ell so as to electrically isolate said region from the epitaxial layer and the substrate.

According to another aspect of the invention there is provided a semiconductor structure, including a semiconductor substrate on a major surface of which an epitaxial layer is disposed, a semiconductor device formed in a region of the epitaxial layer, a well provided in said substrate extending from a surface opposite said one surface substantially to the epitaxial layer and in register with the region, and an annulus of oxidised semiconductor material surrounding said region and extending through the epitaxial layer into said well the annulus isolating the region from the epitaxial layer and the substrate.

An embodiment of the invention will now be described with reference to the accompanying drawing which is a schematic view of a semiconductor device provided with dielectric isolation.

Referring to the drawing, an n +type silicon substrate 11 is provided with an n-type epitaxial layer 12. A well 13 is etched into the substrate from the underside and in a region in register with a region 20 of the epitaxial layer 12 in which a circuit is to be formed, the well extending through the substrate to such a depth as to leave the region 12 of the epitaxial layer and an adjoining thinner region 14 of the underlaying substrate. Using isoplanar techniques a long oxidation is performed to grow a contiguous oxide region 15 throughout the depth of the epitaxial layer and the adjoining thin substrate region 14 so as to completely isolate the device region 12 from the surrounding semiconductor. Typically, a layer of silicon nitride is deposited on the surface of the semiconductor and windows are formed by conventional photolithographic and etching techniques. The oxidation is then performed for several hours in an atmosphere of wet oxygen. The oxidation time and the build up of oxide above the surface can be reduced by first etching a moat in the region where the oxidation is to be performed. As a typical semiconductor device is less than 100 microns square, the oxide region 15 has sufficient strength to support the isolated region 20 of the silicon wafer 12.

The transistor comprising the stages of the amplifier may be formed simultaneously using conventional photolithographic and etching techniques to form windows in an oxide layer (not shown) on the epitaxial layer, a p-type impurity being diffused through the windows. Further windows are made in the oxide layer and through which an n-type impurity is diffused to form the transistors.

A deep n + diffusion extending through the epitaxial layer to the thin substrate region 14 is performed to provide a collector contact of the input transistor. The diffusion time for such a collector contact is relatively long, but the combined times for the diffusion and isolation oxidation is comparable with that for an isoplanar partial dielectric isolation process. Allowance for the outdiffusion from the substrate during this time is made when choosing the thickness of the epitaxial layer 12. Transistors 16 in the isolated wafer and 17 and 18 in the adjacent non-isolated region are then diffused. In a typical linear amplifier arrangement transistor 17 is a Darlington pair driver structure and 18 comprises an output transistor. The transistor in the isolated and non-isolated regions are diffused simultaneously in the conventional manner.

Control of the depth of the well may be effected by the use of a preferential etch which is either orientation or concentration dependent. If the latter is employed an n + diffusion to reduce collectors resistance may be required. In some applications the isolating oxidation process may be performed prior to etching of the underlying substrate.

Claims

WHAT WE CLAIM IS: 1. A method of isolating a semiconductor device formed in a region of an epitaxial semiconductor layer disposed on a major surface of a semiconductor substrate, the method including etching a well into the substrate from a surface opposite the major surface, said well being in register with the region and extending substantially to the epitaxial layer, masking the surface of the epitaxial layer so as to leave an annulus of exposed semiconductor material surrounding said region, and subjecting the masked surface to an oxidation process so as to grow a ring of oxide through the epitaxial layer and into the well so as to electrically isolate said region from the epitaxial layer and the substrate.
2. A method as claimed in claim 1, and wherein said exposed annulus of semiconductor material is etched so as to form a moat around the region prior to the oxidation process.
3. A method as claimed in claim 1, or 2, and in which the substrate is of n ±type silicon on which an n-type epitaxial layer has been deposited.
4. A method as claimed in claim 1, 2 or 3, and which further includes diffusing a first transistor into the isolated region and simul taneously diffusing a second Darlington pair transistor and a third output transistor into adjacent regions of the epitaxial layer so as to form a linear amplifier structure.
5. A semiconductor isolation method substantially as described herein with reference to the accompanying drawing.
6. A semiconductor structure, including a semiconductor substrate on a major surface of which an epitaxial layer is disposed, a semiconductor device formed in a region of the epitaxial layer, a well provided in said substrate extending from a surface opposite said one surface substantially to the epitaxial layer and in register with the region, and an annulus of oxidised semiconductor material surrounding said region and extending through the epitaxial layer into said well, the annulus isolating the region from the epitaxial layer and the substrate.
7. A structure as claimed in claim 6, and semiconductor including a first input transistor, a second Darlington pair driver transistor structure, and a third output transistor, said input transistor being formed in said isolated region, said structure comprising a monolithic linear amplifier.
8. A semiconductor structure substantially as described herein with reference to the accompanying drawing.