GB1558903A - Systems for duplicating digital transmission channels - Google Patents

Description

(54) SYSTEM FOR DUPLICATING DIGITAL TRANSMISSION CHANNELS (71) We, ETAT FRANCAIS, represented by le Secrétaire d'Etat aux Postes et Télécommunications (C. N. E. T.) and TELECOMMUNICATIONS RADIOELECTRO NIQUES ET TELEPHONIQUES of 38, rue du Général Leclerc, 92131 ISSY-LES MOULINEAUX, France and 88, rue Brillat-Savarin, 75640 PARIS CEDEX 13, France respectively, do hereby declare the invention, for which we pray that a Patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:: The present invention concerns a channel duplicating terminal which can be inserted in a transmission path formed by two digital channels connecting two multiplexer-demultiplexer units (muldex units) in order to selectively connect the muldex units to one of said channels according to the transmission quality thereon.

The article entitled "LD-4 Digital Repeatered Line" by M. FRAME, R. KLEDT, W.

MeGEE and D. REID in the American Review "I. E. E. E. International Conference on Communications", June 17-19, 1974, Minneapolis, Minnesota, disclosed a digital transmission system in which a coaxial cable is divided into five working channels and one protection channel in each direction. Traffic on any one of the working channels may be rerouted over the protection channel either automatically, if the performance of a working channel becomes unacceptable, or, for maintenance purposes through manual control of the switching logic.The traffic rerouting is controlled at the receiving end of teach switching section, with a control connection to the transmit end over a particular pair in the coaxial enable. Switching in one direction of traffic is independent of the condition of the channels in the other direction.

Each working channel is monitored for signal failure and high violation rate of the code on line. The protection channel is monitored for the same conditions, and in addition, for the presence or absence of an idle-state signal. This idle-state signal is connected at the transmit end of each section and terminated at the receive end.

Requests from the monitors for a protection switch are processed by the receive end logic, which applies the priority constraints (e.g., a channel with a signal failure has priority over one with a high violation rate) and which transmits a bridge order to the transmit end.

There, the transmit logic disconnects the idle-state signal generator from the protection channel and connects the signal from one port of a hybrid splitter in the working channel.

The disappearance of the idle-state signal on the protection channel indicates to the receive logic that the transmit end bridge has been made. The receive switch is operated to bypass the faulty line section after the signal quality on the protection channel has been checked.

Both working and protection channels now carry the same signal, and the traffic is automatically transferred back when the working channel monitor indicates good performance again.

According to the present invention, there is provided a system for duplicating channels in a digital transmission system wherein two multiplexer and demultiplexer units are connected by two digital transmit and receive channels, the system comprising two duplicating terminals inserted between said two channels and the multiplexer and demultiplexer units and respectively associated with each multiplexer and demultiplexer unit, and, in each of said duplicating terminals. means for normally connecting the transmit parts of the two channels in parallel to the output of the associated multiplexer, devices for monitoring a certain number of faults classified in order to priority and occurring on the receive parts of the channels entering the duplicating terminals, means which when actuated by the fault monitoring device selectively connect the non-faulty channel or the channel faulty with the lower priority order to the associated demultiplexer, and means for replacing the normal connection between the multiplexer unit and the transmit parts of the two channels by a connection between at least one channel transmit part and an alarm return signal generator.

In a system embodying the present invention, switching over does not take place from one among a plurality of working channels to a protection channel proper but between the receive sub-channel of two bidirectional channels according to a receive sub-channel switching over programme derived from the absence or presence of faults detected on said receive sub-channels and the seriousness thereof. No special channel if provided for keeping the transmit end advised of a switching over having occurred at the channel receive end. Normally, the two transmit sub-channels of the bidirectional channels are connected in parallel and switching over therebetween is not provided for except for transmitting to the channel transmit end a special signal indicating that switching over has taken place at the receive end.This transmit sub-channel switching over is made according to a transmit sub-channel switching over programme derived from the absence or presence of faults which can be expected on said transmit sub-channels from the knowledge of the faults detected on the associated receive sub-channels and the seriousness thereof.

During normal operation, the signal from the multiplexer is transmitted along the two channels simultaneously. During reception, only the signal received from the working channel is transmitted to the demultiplexing unit. If one of the two channels is out of action for a long time, the duplicating terminal carries out digital transmission while remaining transparent. By means of this method of forcing, the duplicating terminal can be used when only one channel is available but it is intended to further provide a second. The same method ensures reliability in the case where a channel is repeatedly out of order. The monitoring activity is still carried out. Forcing or initialization can be carried out from either of the two ends.

The duplicating terminal monitors a certain number of faults in the line code signal entering the terminal and coming from the multiplexer or entering the terminal from the line terminals, i.e. faults are monitored at three places. Faults detected at the input of the duplicating terminal connected to the multiplexing unit are used to raise an alarm. If faults are detected at the inputs of the duplicating terminal connected to the line terminals, there is selective switching from one channel to the other. Faults are classified in an order of priority. When a fault is detected in only one channel, the duplicating terminal is connected to the other channel. When faults are detected on both channels simultaneously, switching over from one channel to another occurs or does not occur, depending on the orders of priority of the detected faults.

The detected faults are as follows 1 - High-priority faults, i.e.

Lack of clock signal for at least a predetermined time (LCS) Reception of an alarm indication signal Re(AIS) which originates from a part of the transmission equipment which is different from the duplicating terminals, e.g. from a multiplexer unit which multiplexes into a channel having a higher rate, several channels comprising that connecting the two duplicating terminals or from a demultiplexer unit which performs the converse demultiplexing operation; 2 - Intermediate-priority faults. i.e.

Reception of the alarm return signal Re(ARS) I and 3 - Low-priority faults, i.e.

Error rate exceeding a certain value (ERE). The error rate can be optionally measured, either on the framing word or with respect to violations in bipolarity of the HDBn code used on the digital channels.

Action taken in the event of a fault The two duplicating terminals remain connected to the same channel to which they were initialized, as long as no fault is detected. When a fault is detected on a single channel, the duplicating terminal switches over to the channel which is still in order, if it is not already connected thereto. When faults are detected on both channels, two cases are distinguished.

If the detected faults have the same priority, the duplicating terminal remains connected to the channel to which it was connected before the faults appeared. If the detected faults have different priority, the duplicating terminal is connected to the channel having the lower priority fault.

When a duplicating terminal switches to one of the channels after a fault has been detected on the other, the other duplicating terminal has to be switched over to the same channel. Similarly, when a duplicating terminal detects a fault on the unused channel, the other duplicating terminal has to be informed that the unused channel is unusable. This.is done by using the alarm return signal (ARS), i.e. a repeating bit sequence of variable duration.

The following criteria are used for transmitting an alarm return signal (ARS): - in the event of a fault on a single channel, the alarm return signal is transmitted on the faulty channel (the channel which is recognized to be faulty in the receiving direction); - if faults occur on both channels, the alarm return signal is transmitted along both channels if the faults have high priority, along one faulty channel (faulty in the reception direction) if the faults have low priority, or along the channel having a high-priority fault if the priorities are different.

In tables I and II hereinafter, LCS denotes the lack-of-clock signal; ERE is the signal showing that a given error rate has been exceeded; Re(ARS) is the received alarm return signal; and Re(AIS) is the received alarm indication signal.

Table I shows the channel used when the different fault detection signals occur, and Table II shows the channel along which the alarm return signal (ARS) is transmitted. The symbol (WC) means "without change" : i.e. the previously-used channel remains in operation.

Table I Channel Channel B Forcing in No fault ERE Re(ARS) LCS or Re(AIS) A Service c no fault WC A A A A h a ERE B WC A A A n n Re(ARS) B B WC A A e 1 LCS or Re(AIS) B B B WC A A Forcing B B B B B WC Table II EMISSION Channel B Forcing (ARS) No fault ERE LCS or Re(AIS) A c no fault - B B B h a n ERE A WC B B n e 1 LCS or Re(AIS) A A A and B B A Forcing B A A A WC The invention will now be described in detail with reference to the accompanying drawings, in which: - Figure 1 is a block diagram of a two-channel digital transmission system comprising a channel duplicating system embodying the invention - Figures 2A and 2B are diagrams of a terminal for duplicating digital channels; and - Figure 3 shows the logic circuit included in the terminal for duplicating digital channels and controlling the switching-over from one channel to another.

Figure 1 shows a system for duplicating digital channels comprising two duplicating terminal units 1, 2 disposed between two multiplexing and demultiplexing units 10, 20 and two pairs of line or radio-link terminals 11, 12 and 21 22 respectively. The multiplexing and demultiplexing units are e.g. of the kind converting thirty two 64 kb/s digital channels into a single 2.048 Mb/s digital channel or vice versa. Line terminals 11, 21 and 12, 22 are connected by 4-wire digital lines 91. 92 respectively having a flow rate of 2.048 Mb/s and conveying digital signals in HDBn code, e.g. in HDB 3 code.

The multiplexer and demultiplexer unit 10 and the duplicating terminal 1 are connected by a transmit junction 31 and a receive junction 32 and the duplicating terminal 1 and the line terminals 11, 12 are connected by transmit junctions 51,71 and receive junctions 52, 72.

These junctions are e.g. 6 dB HDB3 junctions. The multiplexer and demultiplexer unit 20, the duplicating terminal 2 and the line terminals 21, 22 are inter-connected by junctions 41, 42, 61, 62, 81, 82 which respectively are similar to junctions 31, 32, 51, 52, 71, 72 Figure 2A shows the junctions 31, 32 between duplicating terminal 1 and multiplexerdemultiplexer 10, transmit junctions 51, 71 with line terminals 11, 12 and receive junctions 52, 72 of line terminals 11, 12 with the duplicating terminal 1. The duplicating terminal 1 comprises three circuits 33-34, 53-54, 73-74 for transmitting and receiving signals respectively towards and from the multiplexer and demultiplexer unit 10, the line terminal 11 and the line terminal 12.The receive circuit 34 is connected via AND gates 343, 345 to the transmit circuits 53, 73 via three-wire junctions 341, 342 permanently connected to one another, and the transmit circuit 33 is connected to the receive circuits 54, 74 by three-wire junctions 331, 332 actuated by AND gates 333, 334. It can be seen that, as stated at the beginning of the description, the multiplexer unit transmits to both channels whereas the demultiplexer unit only receives a single channel selectively. In conventional manner, the receive circuits 34, 54, 74 are used for re-shaping, extracting the clock signal and breaking up the bipolar signal HDB3 into binary signals HDB3+ and HDB3-. In conventional manner likewise, the transmit circuits 33, 53, 73 are used for shaping, timing and combining the binary signals HDB3 and HDB3- into a bipolar signal HDB3.

As shown in Figures 2A and 2B, the wires of junctions 341-342, 331-332 conveying the clock signal and the signals HDB3+ and HDB3- are connected to means 35, 55, 75 respectively, which detect the absence of clock signals and supply an output signal in the case of lack of clock signal. The detecting circuits comprise e.g. integrators followed by inverters. If a lack of clock signal occurs, they supply an output signal which ignites signalling lamps 351, 551, 751 respectively. The output signals of detectors 55, 75 (Figure 2B) are also connected to the logic circuit 100 by leads 552, 752 respectively, to which they apply the lack-of-clock signals LCSA and LCSB.

The connecting wires of junctions 341-342, 331-332 are also connected to means 36 (Figure 2A), 56 and 76 (Figure 2B) for detecting errors involving violation in bipolarity, and to means 38 (Figure 2A), 58 and 78 (Figure 2B) for detecting the alarm indication signal (AIS) and the alarm return signal (ARS) respectively. It is known that, in HDBn codes, no sequence of more than n consecutive zeros can exist. As long as the transmitted binary sequence does not include a sequence containing more than n consecutive zeros, the HDBn code is identical with the bipolar code. However, every sequence of n+1 zeros is converted as soon as it occurs into: either B O . . O V or 0 0.. .0 V where B is a non-zero signal element which respects bipolarity and V is a non-zero signal element which violates polarity.Thus two successive violations always have opposite signs.

Detectors 36, 56, 76 detect the fact that polarity violations do not have alternate signs.

Double bipolarity violation detectors are known in the art, see e.g. the article "Compatible High-Density Bipolar Codes: An Unrestricted Transmission Plan for PCM Carriers" by Alain Croisier, IEEE Transactions on Communications Technology, June 1970, page 266, Figure 3.

If a fault occurs, the detector means 36. 56, 76 for detecting errors involving bipolarity violations supply an output signal which is applied to a counter 37 (Figure 2A) or 57 or 77 (Figure 2B). After a given time, the count in the counter is read by applying a read-out signal provided by time base 9 via connection 901. If the read-out number is greater than a given number, an output signal is produced by the corresponding counter and ignites signalling lamps 371 (Figure 2A), 571 and 771 (Figure 2B), respectively. With reference to Figure 3, counters 57, 77 are also connected to the logic circuit 100, to which they supply error rate exceed signals (ERE)A and (ERE)B via connections 572 and 772.

If required, the rate of errors, instead of being measured by violations of bipolarity, can be measured with respect to the framing word, which is received in circuits 156, 176 for detecting errors in the framing words, via switches 157 and 177. These error-detecting circuits are well known in the art and usually comprise a register which receives the word in which errors are to be detected. inverters at the output of only those stages in the register which receives zeros (or units) and an AND gate or a NAND gate receiving indentical bits from all the register stages and producing an output signal when the bits are not identical.

The outputs of detector circuit 156, 176 are connected to counters 57, 77 respectively by switches 158, 178. Finally, since counter 57 is read after one period of time when the error detector 56 is used and after another period when the error detector 156 is used, the time base produces square waves on a line 902, the square waves having a different duration from those produced on wire 901, and a switch 159 or 179 is selectively used for switching counter 57 or 77 to wires 9G1, 902. It can be seen that when switches 157, 158, 159 (or 177, 178, 179) are positioned at the left, as shown in Figure 2B, the error detectors 56 (or 76) are in operation, whereas when the switches are positioned on the right, error detectors 156 (or 176) are in operation.

As a further detail, in a digital channel duplicating system constructed by the Applicants, a means for detecting errors in the framing words is adjusted to obtain an alarm signal if there are more than 7 errors in 4.1 s+20So, and a detector of errors consisting of violations in bipolarity is adjusted to obtain an alarm signal if there are more than 256 errors in 1.25 si20%. This corresponds to an error rate of 10-4 in both cases.

The alarm return (ARS) and alarm indication (AIS) signals are sequences of bits having a variable duration; for example, the alarm return signal is formed from the sequence 0 1 0 1.

. and the alarm indication signal is formed from the sequence 1 1 11 . . . These alarm return and alarm indication sequences are detected by detectors 38 (Figure 2A), 58 and 78 (Figure 2B) connected to the connecting wires of the junctions 341-342, 331-332 respectively. Means for detecting special sequences are known in the art and need not be described in detail. The output signals of detectors 38, 58 and 78 corresponding to reception of the alarm return signal (ARS) and the alarm indication sequence (AIS) are applied to pairs of counters 39 (Figure 2A), 59 and 79 (Figure 2B) in which the counts are read after a certain time. If the read-out count does not exceed a given value, an output signal is produced by the corresponding counter.The output signals of pairs of counters 39, 59 and 79 ignite lamps 391 (ARS), 591 (ARS)A, 791 (ARS)B, 392 (AIS), 592 (AIS)A, 792 (AIS)B respectively and the output signals of pairs of counters 59 and 79 are applied to logic circuit via wires 593 (ARS)A, 793 (ARS)B, 594 (AIS)A, 794 (AIS)B respectively.

The counting periods of counters 59 and 79, between switchingon and stopping, are fixed by the square waves delivered by time base 9 along wires 903 and 904. For example, in the digital channel duplicating system constructed by the Applicants, a means for detecting the alarm indication signal and the alarm return signal operated either for periods of 500 ,us or for periods of 1.25 s.

Figure 3 shows the logic circuit 100. The circuit has eight input connections 552 (LCS)A, 752 CLCS)B, 572 (ERE)A, 772 (ERE),, 593 (ARS)A, 793 (ARS)n, 594 (AIS)A, 794 (AIS)n, plus two forcing inputs 595 (FCnd and 795 (FC)B cntrolled by hand and three outputs 1003-1004, 1001-1001 and 1002-1002.

The logic circuit 100 comprises three priority and exclusion circuits 101, 102,103 which are identical; only the first circuit 101 is shown in detail. High-priorit signals (LCS)A, (AIS)A are combined in a NOR gate 1005 and high-priority signals (LCS)B and (AIS)B are combined in a NOR gate 1006. The outputs of these two gates are both inputs of the priority and exclusion circuit 101. The forcing signals (FC)A and (FC)B are applied to two NOR gates 1007 and 1008; the second input of gate 1007 is connected to the output of gate 1008 and, symmetrically, the second input of gate 1008 is connected to the output of gate 1007.

The outputs of NOR gates 1007 and 1008 are the two other inputs of priority and exclusion circuit 101.

Priority and exclusion circuit 101 comprises two NOR gates 1011 and 1012 which receive the lower priority signals (LCS)+AIS)A and (LCS) + (AIS)B and two OR gates 1013 and 1014 which receive the higher priority signals (FC)A and (FC)B. The second inputs of NOR gates 1011 and 1012 are connected respectively to the outputs of OR gates 1014 and 1013 and the second inputs of OR gates 1013 and 1014 are connected to the outputs of NOR gates 1011 and 1012. When a lower priority fault is detected, the corresponding fault signal is 0 and when a higher priority fault is detected, the corresponding fault signal is 1.

Denoting by 1011, 10112. 1012" 10122 the inputs to circuit 101 respectively receiving signals (LCS) + (AIS)A, (FC)B, (FC)A, (LCS) + (AIS)B and by 10131 and 10141, the outputs of circuit 101, one can draw the following table a b c d e 10111 1 X X 0 1 10112 0 1 0 0 0 10121 0 0 1 0 0 10122 1 X X 1 0 10131 0 1 0 1 0 10141 0 0 1 0 1 X = irrelevant a = no fault at all b = a fault on (FC)B i.e. forcing channel B c = a fault on (FC)A i.e. forcing channel A d = a fault on (LCS)A or (AIS)A e = a fault on (LCS)B or (AIS)B It must be noticed that (FC)A and (FC)B cannot be both equal to 1 since there is a R-S tvpe flipflon 1007-1008 before circuit 101. When (LCS)A + (AIS)A being equal to O, (LCS)B + (AIS), becomes also equal to 0. no change is induced in the output signals.

When (LCS)A + (AIS)A and (LCS)B + (AIS)B being both equal to 0, one of them switches over to 1, no change is induced in the output signals.

Priority and exclusion circuit 102 is identical to circuit 101; its four inputs respectively receive the two output signals of circuit 101 and (ARS)A and (ARS)B. Priority and exclusion circuit 103 is identical to circuits 101 and 102; its four inputs respectively receive the two output signals of circuit 102 and (ERE)A and (ERE)B. The outputs of circuit 103 are connected to a R-S type flip-flop formed by two NOR gates 1009 and 1010 with crossed connections as it is well known. The outputs of this R-S type flipflop control the AND gates 333 and 334 (Figure 2A) through leads 1003 and 1004 respectively.

Signals (LCS)A + (AIS)A, (LPS)B = (AIS)B and (FC)A and (FC)B are applied to a priority circuit 1U4 hollowed by a priority and exclusion circuit 105. Priority circuit 104 is formed by two NOR gates 1041 and 1042 and two OR gates 1043 and 1044. The signals (FC)A and (FC)B applied to gates 1043 and 1044 have the higher priority. If one channel is forced, e.g. channel A, (FC)A = 1 and a 1 is collected at the output of 1044. As the output signal from gate 1044 controls the sending of the alarm return signal on channel 92(B), it can be seen that, in the case of forcing, signal (ARS) is sent on the non-forced channel.If there is a high priority fault on the two channels, (LCS)A + (AIS) and (LCS)13 + (AIS) B are both equal to zero and a 1 is collected at the outputs ot 1043 and 1044.

The alarm return signal is sent on both channels 91(A) and 92(B).

Priority and exclusion circuit 105 is identical to circuit 101 and comprises two NOR gates 1051 and 1052 and two OR gates 1053 and 1054. The signal (ERE)A and (ERE)B of lower priority are given the higher priority and are applied to NOR gates 1051 and 1052. It can be seen that, in the case of faults of lower priority on both channels (91)A and 91(B), (ERE)A and (ERE)n are equal to 1 and the alarm return signal is sent on the first out of order circuit. If the faults have different priorities, the alarm return signal is sent on the channel the fault of which has the higher priority.

The outputs of circuit 105 are connected to OR gates 1061 and 1062 on the one hand directly and on the other hand through a delay circuit, respectively 1063 and 1064, which gives to the alarm return signal a duration at least equal to the delay of circuit 1063 and 1064.

The output signal of OR gate 1061 controls through leads 1001 and 1001 AND gates 343 and 344 (Figure 2A) and the output signal of OR gate 1062 controls through leads 1002 and 1002 AND gates 345 and 346 (Figure 2A). AND gates 343 and 345 connect the multiplexer unit to the digital channels through leads 341 and 342 and AND gates 344 and 346 connect the alarm return signal generator 107 to the digital channels.

WHAT WE CLAIM IS: 1. A system for duplicating channels in a digital transmission system wherein two multiplexer and demultiplexer units are connected by two digital transmit and receive channels, the system comprising two duplicating terminals inserted between said two channels and the multiplexer and demultiplexer units and respectively associated with each multiplexer and demultiplexer unit, and, in each of said duplicating terminals, means for normally connecting the transmit parts of the two channels in parallel to the output of the associated multiplexer, devices for monitoring a certain number of faults classified in order of priority and occurring on the receive parts of the channels entering the duplicating terminals, means which when actuated by the fault monitoring devices selectively connect the non-faulty channel or the channel faulty with the lower priority order to the associated demultiplexer, and means for replacing the normal connection between the multiplexer unit and the transmit parts of the two channels by a connection between at least one channel transmit part and an alarm return signal generator.

2. A system for duplicating channels in a digital transmission system according to claim 1, in which the means for monitoring a certain number of faults occurring on the receive parts of the channels comprises at least high-priority means for monitoring the absence of a clock signal and for producing a first signal when the above-mentioned absence exceeds a given time, and low-priority means for monitoring errors occurring in the code used on the digital channels and producing a second signal when the errors exceed a certain number per unit time, and wherein the means for selectively connecting the non-faulty channel or the channel faulty with the lower priority order to the demultiplexer and the means for

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (8)

**WARNING** start of CLMS field may overlap end of DESC **. a = no fault at all b = a fault on (FC)B i.e. forcing channel B c = a fault on (FC)A i.e. forcing channel A d = a fault on (LCS)A or (AIS)A e = a fault on (LCS)B or (AIS)B It must be noticed that (FC)A and (FC)B cannot be both equal to 1 since there is a R-S tvpe flipflon 1007-1008 before circuit 101. When (LCS)A + (AIS)A being equal to O, (LCS)B + (AIS), becomes also equal to 0. no change is induced in the output signals. When (LCS)A + (AIS)A and (LCS)B + (AIS)B being both equal to 0, one of them switches over to 1, no change is induced in the output signals. Priority and exclusion circuit 102 is identical to circuit 101; its four inputs respectively receive the two output signals of circuit 101 and (ARS)A and (ARS)B. Priority and exclusion circuit 103 is identical to circuits 101 and 102; its four inputs respectively receive the two output signals of circuit 102 and (ERE)A and (ERE)B. The outputs of circuit 103 are connected to a R-S type flip-flop formed by two NOR gates 1009 and 1010 with crossed connections as it is well known. The outputs of this R-S type flipflop control the AND gates 333 and 334 (Figure 2A) through leads 1003 and 1004 respectively. Signals (LCS)A + (AIS)A, (LPS)B = (AIS)B and (FC)A and (FC)B are applied to a priority circuit 1U4 hollowed by a priority and exclusion circuit 105. Priority circuit 104 is formed by two NOR gates 1041 and 1042 and two OR gates 1043 and 1044. The signals (FC)A and (FC)B applied to gates 1043 and 1044 have the higher priority. If one channel is forced, e.g. channel A, (FC)A = 1 and a 1 is collected at the output of 1044. As the output signal from gate 1044 controls the sending of the alarm return signal on channel 92(B), it can be seen that, in the case of forcing, signal (ARS) is sent on the non-forced channel.If there is a high priority fault on the two channels, (LCS)A + (AIS) and (LCS)13 + (AIS) B are both equal to zero and a 1 is collected at the outputs ot 1043 and 1044. The alarm return signal is sent on both channels 91(A) and 92(B). Priority and exclusion circuit 105 is identical to circuit 101 and comprises two NOR gates 1051 and 1052 and two OR gates 1053 and 1054. The signal (ERE)A and (ERE)B of lower priority are given the higher priority and are applied to NOR gates 1051 and 1052. It can be seen that, in the case of faults of lower priority on both channels (91)A and 91(B), (ERE)A and (ERE)n are equal to 1 and the alarm return signal is sent on the first out of order circuit. If the faults have different priorities, the alarm return signal is sent on the channel the fault of which has the higher priority. The outputs of circuit 105 are connected to OR gates 1061 and 1062 on the one hand directly and on the other hand through a delay circuit, respectively 1063 and 1064, which gives to the alarm return signal a duration at least equal to the delay of circuit 1063 and 1064. The output signal of OR gate 1061 controls through leads 1001 and 1001 AND gates 343 and 344 (Figure 2A) and the output signal of OR gate 1062 controls through leads 1002 and 1002 AND gates 345 and 346 (Figure 2A). AND gates 343 and 345 connect the multiplexer unit to the digital channels through leads 341 and 342 and AND gates 344 and 346 connect the alarm return signal generator 107 to the digital channels. WHAT WE CLAIM IS:

1. A system for duplicating channels in a digital transmission system wherein two multiplexer and demultiplexer units are connected by two digital transmit and receive channels, the system comprising two duplicating terminals inserted between said two channels and the multiplexer and demultiplexer units and respectively associated with each multiplexer and demultiplexer unit, and, in each of said duplicating terminals, means for normally connecting the transmit parts of the two channels in parallel to the output of the associated multiplexer, devices for monitoring a certain number of faults classified in order of priority and occurring on the receive parts of the channels entering the duplicating terminals, means which when actuated by the fault monitoring devices selectively connect the non-faulty channel or the channel faulty with the lower priority order to the associated demultiplexer, and means for replacing the normal connection between the multiplexer unit and the transmit parts of the two channels by a connection between at least one channel transmit part and an alarm return signal generator.

2. A system for duplicating channels in a digital transmission system according to claim 1, in which the means for monitoring a certain number of faults occurring on the receive parts of the channels comprises at least high-priority means for monitoring the absence of a clock signal and for producing a first signal when the above-mentioned absence exceeds a given time, and low-priority means for monitoring errors occurring in the code used on the digital channels and producing a second signal when the errors exceed a certain number per unit time, and wherein the means for selectively connecting the non-faulty channel or the channel faulty with the lower priority order to the demultiplexer and the means for

replacing the normal connection between the multiplexer and the transmit parts of the two channels by a connection between at least one channel transmit part and an alarm return signal generator are actuated by the aforementioned first and second signals.

3. A system of duplicating channels in a digital transmission system according to claim 2, wherein the cdde used on the digital channels in an HDBn code and the low-priority means for monitoring errors occurring in the code used on the digital channels comprises a detector of errors involving violation of bipolarity.

4. A system for duplicating channels in a digital transmission system according to claim 2, wherein the signals used on the digital channels are signals multiplexed in frames with framing words and the low-priority means for monitoring errors occurring in the code used on the digital channels comprises a means for detecting errors in the framing words.

5. A system for duplicating channels in a digital transmission system according to claim 2, in which the means for monitoring a certain number of faults occurring on the receive parts of the channels comprises intermediate-priority means for detecting the alarm return signal transmitted by the other duplicating terminal, in addition to the high-priority means for monitoring the absence of a clock signal and the low-priority means for monitoring errors occurring in the code used on the digital channels.

6. A system of duplicating channels in a digital transmission system according to claim 2, in which the duplicating channels comprise means for supplying them with signals for forcing one or the other digital channel, the forcing signals being considered to have the highest priority.

7. A system for duplicating channels in a digital transmission system according to claim 2, in which the means for monitoring a certain number of faults occurring on the receive parts of the channels comprises the high-priority means for monitoring the absence of a digital transmission clock signal, the intermediate-priority means for detecting the alarm return signal transmitted by the other duplicating terminal and the low-priority means for monitoring errors occurring in the code used on the digital channels, and also comprises high-priority means for detecting an alarm indication signal produced by a circuit inserted in the digital channels between the two multiplexer and demultiplexer units.

8. A system for duplicating channels in a digital transmission system substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.