JPS6133418B2 - - Google Patents

Info

Publication number
JPS6133418B2
JPS6133418B2 JP54004566A JP456679A JPS6133418B2 JP S6133418 B2 JPS6133418 B2 JP S6133418B2 JP 54004566 A JP54004566 A JP 54004566A JP 456679 A JP456679 A JP 456679A JP S6133418 B2 JPS6133418 B2 JP S6133418B2
Authority
JP
Japan
Prior art keywords
code
line
circuit
transmission line
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54004566A
Other languages
Japanese (ja)
Other versions
JPS5596744A (en
Inventor
Kunyuki Nagai
Kazuhisa Hatsutori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Signal Co Ltd
Original Assignee
Nippon Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority to JP456679A priority Critical patent/JPS5596744A/en
Publication of JPS5596744A publication Critical patent/JPS5596744A/en
Publication of JPS6133418B2 publication Critical patent/JPS6133418B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/24Testing correct operation

Landscapes

  • Small-Scale Networks (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Description

【発明の詳細な説明】 この発明は、親装置とこれに伝送回線を介して
マルチドロツプ式に接続されれた複数個の子装置
と、さらに親装置と端末子装置間を前記伝送回線
と切換可能に別回線で直結してなる符号送受信装
置において、雑音の混入による不良回線の自動切
離し装置の改良に関するもので、切離した回線を
自動的に復旧させるようにしたこの種装置の提供
を目的とするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a parent device and a plurality of child devices connected to the parent device via a transmission line in a multi-drop manner, and further enables switching between the parent device and terminal child devices using the transmission line. This invention relates to an improvement in a device for automatically disconnecting a defective line due to noise in a code transmitting/receiving device that is directly connected to a separate line by a separate line, and its purpose is to provide this type of device that automatically restores a disconnected line. It is something.

上記符号送受信装置における不良回線自動切離
し装置に関しては、すでに本件出願人と同一人の
出願に係わる特願昭51―156907号(特開昭53―
80111号公報)の明細書においてその詳細が述べ
られているが、本発明は前記特許願の発明にさら
に効果ある改良を施したものである。従つて本発
明を説明する前提として前記特許願の発明の概要
を述べると、まず上記符号送受信装置において、
複数個の子装置をマルチドロツプ式に親装置に接
続する伝送回線を常用回線と称し、親装置と端末
子装置とを直結する回線を迂回回線と称するが、
この迂回回線は常用回線が万一断線して装置がシ
ステムダウンに陥るのを防止するためのもので、
親装置における符号の送受信に常用と迂回の両回
線を切換え可能に設備されている。また常用、迂
回の両回線とも親装置から子装置への符号伝送方
向を下流と呼び、子装置から親装置への伝送方向
を上流と称している。
Regarding the defective line automatic disconnection device in the above-mentioned code transmitting/receiving device, Japanese Patent Application No. 51-156907 (Japanese Unexamined Patent Application Publication No. 1983-1988) filed by the same applicant as the present applicant has already been filed.
Although the details are described in the specification of Japanese Patent Application No. 80111, the present invention is a further effective improvement of the invention of the above-mentioned patent application. Therefore, as a premise for explaining the present invention, an outline of the invention of the above patent application will be described. First, in the above code transmitting/receiving device,
A transmission line that connects multiple child devices to a parent device in a multi-drop manner is called a regular line, and a line that directly connects the parent device and terminal child devices is called a detour line.
This detour line is intended to prevent the equipment from going down due to a disconnection of the regular line.
The parent device is equipped to be able to switch between regular and detour lines for transmitting and receiving codes. Further, for both regular and detour lines, the direction of code transmission from the parent device to the child device is called downstream, and the direction of code transmission from the child device to the parent device is called upstream.

上述のようにして、常用回線の断線によるシス
テムダウンの防止策は講じられていたが、さらに
伝送回線に雑音が混入して引き起されるシステム
ダウンの防止策として提供されたのが上記特許願
の発明「不良回線自動切離し装置」である。すな
わち第1図は同図に示す破線のブロツク内に前記
切離し装置を施した状態を子装置の代表として示
した任意の子装置Biを含む子装置群B(i―
1),B(i+1)等および端末子装置Bnをマル
チドロツプ式に親装置Mに接続する常用の下流回
線MLD、上流回線MLUおよび親装置Mと端末子
装置Bnとを直結する迂回の下流回線PLD、上流
回線PLU等で構成される符号送受信装置のブロ
ツク図で、上記特許願の不良回線自動切離し装置
は、子装置Biの内部に示す符号判定器DTD,
DTU、接点の図示記号で表わしたスイツチSWD
1,SWD2,SWU1,SWU2、ハイブリツドト
ランスHYB1,HYB2、復帰押ボタンスイツチ
PBD,PBU等から構成されている。
As mentioned above, measures have been taken to prevent system failure due to disconnection of the regular line, but the above patent application was provided as a further preventive measure against system failure caused by noise entering the transmission line. invention of the ``defective line automatic disconnection device.'' That is, FIG. 1 shows a child device group B (i-
1), a regular downstream line MLD that connects B(i+1), etc. and terminal child device Bn to the parent device M in a multi-drop manner, an upstream line MLU, and a detour downstream line PLD that directly connects the parent device M and the terminal child device Bn. , a block diagram of a code transmitting/receiving device consisting of an upstream line PLU, etc. The defective line automatic disconnection device of the above patent application includes a code judger DTD shown inside the child device Bi,
Switch SWD represented by DTU and contact symbols
1, SWD2, SWU1, SWU2, hybrid transformer HYB1, HYB2, return push button switch
It consists of PBD, PBU, etc.

なお、下流方向受信回路R1、上流方向受信回
路R2、送信回路S、論理回路LG等は子装置本
来の回路である。
Note that the downstream receiving circuit R1, the upstream receiving circuit R2, the transmitting circuit S, the logic circuit LG, etc. are the original circuits of the child device.

スイツチSWD1,SWD2,SWU1,SWU2
等は常時は何れも閉成されていて、子装置Biでの
符号の送受が行なわれるが、いま子装置BiとB
(i−1)間の常用回線MLDのa点に雑音が混入
したとすると、この雑音はスイツチSWD2、ハ
イブリツドトランスHYB1、スイツチSWD1を
介して下流の子装置に伝播されると同時に子装置
Biの受信回路R1に受信され、符号判定器DTD
で雑音と判定されると、その判定出力でまずスイ
ツチSWD1を開放して、それより下流の子装置
にそれ以上に雑音が流入するのを防止する。スイ
ツチSWD1は設定された一定時間後に自動的に
閉成されるが、a点に隣接する子装置Biのスイツ
チSWD2はスイツチSWD1の開放後もなお閉成
されていて雑音は受信回路R1に流入するため、
符号判定器DTDから再度雑音判定出力が出てス
イツチSWD2を開放する。この状態は押ボタン
スイツチPBDの復帰扱いがあるまで保持される。
Switch SWD1, SWD2, SWU1, SWU2
etc. are normally closed and codes are sent and received by the child device Bi, but now the child devices Bi and B
Suppose that noise enters point a of the regular line MLD between
Bi is received by the receiving circuit R1, and the sign determiner DTD
If it is determined that the noise is noise, first the switch SWD1 is opened using the output of the determination, thereby preventing further noise from flowing into the downstream slave devices. Switch SWD1 is automatically closed after a set fixed time, but switch SWD2 of child device Bi adjacent to point a is still closed even after switch SWD1 is opened, and noise flows into receiving circuit R1. For,
A noise judgment output is output again from the sign judgment device DTD and the switch SWD2 is opened. This state is maintained until the push button switch PBD is reset.

一方、子装置B(i+1)以降の子装置では前
方の子装置BiのスイツチSWD1が開くことによ
り受信入力が停止されるので、前述の如き再度雑
音判定出力が出ることはなく、各子装置のスイツ
チSWD2は閉成されたまゝである。このように
してa点を含む不良回線はa点に隣接する子装置
BiのスイツチSWD2で切離され、以降の子装置
への雑音の混入が防止される。
On the other hand, for the slave devices after slave device B(i+1), the reception input is stopped by opening the switch SWD1 of the front slave device Bi, so the noise judgment output will not be output again as described above, and each slave device Switch SWD2 remains closed. In this way, the faulty line including point a is connected to the child device adjacent to point a.
It is disconnected by switch SWD2 of Bi to prevent noise from being mixed into subsequent child devices.

以上が上記特許願の発明の概要である。該発明
ではいつたん回線を切離した後の雑音障害復旧後
に再び回線を接続するためには、現地で押ボタン
スイツチ(PBDまたはPBU)を操作してスイツ
チ(SWD2またはSWU2)を閉成させるように
していた。このことは該発明の狙いが、迂回回線
併設の装置の場合、雑音の妨害に際しては、こと
さらに常用回線を断線状態に導き、迂回回線を活
用して装置の動作を確保することにあつて、断線
した回線の復旧を必ずしも緊急事とは考えなかつ
た思想に基づいていた。
The above is an outline of the invention of the above patent application. In this invention, in order to reconnect the line after the noise fault is recovered after disconnecting the line, the switch (SWD2 or SWU2) is closed by operating a push button switch (PBD or PBU) at the site. was. This means that in the case of a device equipped with a detour line, the purpose of the invention is to bring the regular line to a disconnection state in the event of noise interference, and to utilize the detour line to ensure the operation of the device. It was based on a philosophy that did not necessarily consider the restoration of downed lines to be an emergency.

本発明は上記特許願の発明における不良回線切
離し用スイツチの数を半減させると共に雑音が子
装置の論理回路に流入するのを抑止する措置を講
じ、さらに雑音障害の復旧時には切離した回線を
自動的に接続するようにしたものである。
The present invention reduces the number of defective line disconnection switches in the invention of the above patent application by half, takes measures to prevent noise from flowing into the logic circuit of a slave device, and furthermore, automatically disconnects the disconnected line when a noise problem is restored. It was designed to connect to.

以下本発明の実施例を第2図,第3図によつて
説明すると、第2図の2点鎖線で囲んだブロツク
Bkは本発明による改良を施した子装置Bkの構成
を示す回路ブロツク図で、子装置B(k−1)、
B(k+1)も同様の構成であることは勿論であ
る。同図のH1〜H5は何れもハイブリツドトラ
ンス、SW1は下流常用回線MLDに挿入されてい
る回線切離し用スイツチ、SW2は上流常用回線
MLUに挿入されている回線切離し用スイツチ、
DT1はスイツチSW1の開閉を制御する受信符
号判定回路、DT2はスイツチSW2の開閉を制
御する受信符号判定回路、AG1,AG2は論理回
路LGに雑音が流入するのを防止するアンドゲー
トである。なお論理回路LG、受信回路R1,R
2、送信回路Sは第1図と同様子装置本来の回路
である。
Embodiments of the present invention will be explained below with reference to FIGS. 2 and 3. The blocks surrounded by the two-dot chain line in FIG.
Bk is a circuit block diagram showing the configuration of a child device Bk improved according to the present invention, in which child devices B(k-1),
Of course, B(k+1) also has a similar configuration. In the figure, H1 to H5 are all hybrid transformers, SW1 is a line disconnection switch inserted in the downstream regular line MLD, and SW2 is the upstream regular line.
A line disconnection switch inserted in the MLU,
DT1 is a reception code determination circuit that controls the opening and closing of the switch SW1, DT2 is a reception code determination circuit that controls the opening and closing of the switch SW2, and AG1 and AG2 are AND gates that prevent noise from flowing into the logic circuit LG. In addition, logic circuit LG, reception circuit R1, R
2. The transmitting circuit S is the original circuit of the child device as in FIG.

第3図は受信符号判定回路DT1またはDT2の
構成例を示す内部回路のブロツク図で、1は受信
符号を計数するカウンタ、その出力計数値kとl
ではk<lであり、kは正常コードのビツト数に
等しい。2は受信符号各ビツトの論理値“1”と
“0”とを判別する受信符号判別回路、3は受信
した一連の符号に対して必要な照査、例えばパリ
テイチエツク、定マークチエツク、反復チエツク
などを行なうコード検定回路で、照査合格のとき
はg信号、不合格のときはng信号を出力する。
4はオアゲート5を介してコード検定回路3から
のng信号または受信符号カウンタ1からの計数
信号lの回数を計数する不良回数カウンタ、6は
コード検定回路3からのg信号を計数する正常回
数カウンタで、カウンタ4と6の歩進信号はまた
相互のカウンタのリセツト信号として使用され、
さらに前記の両歩進信号はオアゲート7を介して
共に受信符号カウンタ1のリセツト信号となる。
8は不良回数カウンタ4の計数値信号nでセツト
せられ、オア回路9を介する正常回数カウンタ6
の計数値信号mでリセツトされるフリツプフロツ
プで、このフリツプフロツプ8のセツト出力がス
イツチSWの接点を開離させる。10は一定時隔
(一般には数ビツト長)以上受信符号の立上りが
ないとコード終了信号をコード検定回路3に出力
するコード終了検出回路、11は一定時隔(一般
には数コード長)以上受信符号の立上りが検出さ
れないと無信号検出信号を出しオアゲート9を介
してフリツプフロツプ8をリセツトする回線無信
号検出回路である。
FIG. 3 is a block diagram of an internal circuit showing an example of the configuration of the received code determination circuit DT1 or DT2, in which 1 is a counter for counting received codes, and its output count values k and l.
Then k<l, and k is equal to the number of bits of the normal code. 2 is a received code discrimination circuit that discriminates between the logical value "1" and "0" of each bit of the received code; 3 is a necessary check for the series of received codes, such as parity check, fixed mark check, and repetition check; This code verification circuit outputs a g signal when the test passes, and an ng signal when it fails.
4 is a defective number counter that counts the number of times the ng signal from the code verification circuit 3 or the count signal l from the received code counter 1 is received via the OR gate 5; 6 is a normal number counter that counts the g signal from the code verification circuit 3; The increment signals of counters 4 and 6 are also used as a reset signal for each counter,
Furthermore, both of the above-mentioned step signals pass through the OR gate 7 and become a reset signal for the received code counter 1.
8 is set by the count value signal n of the defective number counter 4, and is sent to the normal number counter 6 via the OR circuit 9.
The set output of the flip-flop 8 opens the contacts of the switch SW. 10 is a code end detection circuit that outputs a code end signal to the code verification circuit 3 if there is no rising edge of the received code for more than a certain time interval (generally several bits long), and 11 is a code end detecting circuit that receives data for more than a certain time interval (generally several code lengths). The line no-signal detection circuit outputs a no-signal detection signal and resets the flip-flop 8 via the OR gate 9 when the rising edge of the code is not detected.

上記第3図の回路構成は第2図の受信符号判定
回路DT1,DT2に共通のもので、入力信号Cが
受信回路R1から供給されればDT1として動作
しスイツチSW1の開閉を制御すると共に、その
コード検定合格信号gを条件にアンドゲートAG
1を介して受信信号が論理回路LGに供給され
る。同様にDT2として動作するときはスイツチ
SW2を制御し、受信回路R2の受信信号がアン
ドゲートAG2を介して論理回路LGに供給され、
雑音の流入を阻止する。
The circuit configuration shown in FIG. 3 is common to the reception code determination circuits DT1 and DT2 shown in FIG. And gate AG on condition of that code test pass signal g
1, the received signal is supplied to the logic circuit LG. Similarly, when operating as DT2, switch
SW2 is controlled, and the reception signal of the reception circuit R2 is supplied to the logic circuit LG via the AND gate AG2.
Prevents noise from entering.

つぎに第3図の回路における雑音検出の主要動
作について述べると、入力する雑音が断続的な場
合は、断続波の断の都度コード検定回路3から不
合格信号ngが出力し、不良回数カウンタ4がn
回の不良コードngを連続受信すると、カウンタ
4のn計数値出力がフリツプフロツプ8をセツト
してそのセツト出力によりスイツチSWを開放動
作させる。また雑音が連続的な場合は受信符号カ
ウンタ1が計数値lまでを受信する都度不良回数
カウンタ4が歩進し、l×nビツト受信するとカ
ウンタ4の計数値がnまで進んで、その出力がフ
リツプフロツプ8をセツトしスイツチSWを開放
動作させる。セツトされたフリツプフロツプ8を
リセツトしてスイツチSWを閉成状態に復旧させ
るには、正常コードを連続してm回受信し、正常
回数カウンタ6の計数値がmになつたときの出力
か、一定時間以上受信符号がないことを検出する
回線無信号検出回路11の検出出力かの何れかに
よつて行なわれる。なお不良回数カウンタ4の出
力計数値n、正常回数カウンタ6の出力計数値m
の設定は回線の品質、情報発生頻度等を考慮して
行なわれることは勿論である。また、上記説明は
伝送方向の異なる二つの回線、さらには常用回線
と迂回回線とを有する場合について述べたが、本
発明はこれに限られるものではなく、伝送方向の
定つた一本の回線だけの場合であつても適用でき
ることは勿論である。
Next, to describe the main operation of noise detection in the circuit shown in Fig. 3, when the input noise is intermittent, a failure signal ng is output from the code verification circuit 3 each time the intermittent wave is interrupted, and the failure signal ng is output from the failure frequency counter 4. is n
When the fault code ng is continuously received, the n count value output of the counter 4 sets the flip-flop 8, and the set output causes the switch SW to open. In addition, if the noise is continuous, the failure count counter 4 increments each time the received code counter 1 receives up to a count value l, and when l×n bits are received, the count value of the counter 4 advances to n, and its output is Set the flip-flop 8 and open the switch SW. In order to reset the set flip-flop 8 and restore the switch SW to the closed state, the normal code is received m times in a row, and the output when the count value of the normal number counter 6 reaches m is fixed. This is performed using either the detection output of the line no-signal detection circuit 11 which detects that there is no received code for a period of time or more. Note that the output count value n of the defective number counter 4 and the output count value m of the normal number counter 6
Needless to say, the settings are made taking into account the quality of the line, the frequency of information generation, etc. In addition, although the above description has been made regarding the case where there are two lines with different transmission directions, and furthermore, a regular line and a detour line, the present invention is not limited to this, and the present invention is not limited to this, but only with one line with a fixed transmission direction. Of course, it can be applied even in the case of

以上述べた如く本発明によれば不良検知出力が
一定時間検出されないか、または一定回数連続し
て正常符号を受信したとき、いつたん切離された
回線は自動的に再び接続されるから、雑音による
障害の復旧後現地で復帰押ボタンを操作する手数
が省け、さらに既述のように回線に挿入されるス
イツチ数を半減させたことにより装置の信頼度を
向上させるなど従来のこの種装置に比し格段の効
果を奏するものである。
As described above, according to the present invention, when a fault detection output is not detected for a certain period of time or when a normal code is received a certain number of times in succession, the disconnected line is automatically reconnected, so noise is generated. This saves the trouble of operating the reset button on-site after recovery from a failure, and as mentioned above, the number of switches inserted into the line has been halved, improving the reliability of the equipment. It has a much more effective effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の不良回線自動切離し装置を子装
置に施した概要を示す符号送受信装置のブロツク
図、第2図は本発明回線切離し装置の実施例を符
号送受信装置の子装置に施した回路ブロツク図、
第3図は同上回線切離しスイツチを制御する受信
符号判定回路のブロツク図である。 MLD…下流常用回線、MLU…上流常用回線、
Bk,B(k−1)、B(k+1)…子装置、H1
〜H5…ハイブリツドトランス、SW1,SW2
…常閉スイツチ、DT1,DT2…符号判定回路、
AG1,AG2…アンドゲート、1…受信符号カウ
ンタ、3…コード検定回路、4…不良回数カウン
タ、6…正常回数カウンタ、8…スイツチ制御の
フリツプフロツプ、11…一定時隔無信号検出回
路。
Fig. 1 is a block diagram of a code transmitting/receiving device showing an overview of a conventional faulty line automatic disconnection device applied to a child device, and Fig. 2 is a circuit diagram in which an embodiment of the line disconnection device of the present invention is applied to a child device of the code transmitting/receiving device. block diagram,
FIG. 3 is a block diagram of a received code determination circuit that controls the line disconnection switch. MLD…downstream regular line, MLU…upstream regular line,
Bk, B(k-1), B(k+1)...child device, H1
~H5...Hybrid transformer, SW1, SW2
...Normally closed switch, DT1, DT2...Sign determination circuit,
AG1, AG2...AND gate, 1...Received code counter, 3...Code verification circuit, 4...Failure number counter, 6...Normal number counter, 8...Switch controlled flip-flop, 11...Circumstance interval no-signal detection circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 伝送方向が定められている伝送回線を介して
親装置と複数の子装置を縦続接続した符号送受信
装置において、各子装置ごとに、伝送回線からの
受信符号が所定のフオーマツトであるか否かを判
定して異常符号の連続受信回数及び正常符号の連
続受信回数を検出する符号判定回路と、当該子装
置の信号受信点下流に位置して伝送回線に直列に
挿入接続され、かつ前記符号判定回路が所定回数
だけ異常符号を連続受信したことを条件に伝送回
線を遮断すると共に所定回数だけ正常符号を連続
受信するか又は一定時間以内に亘つて受信符号無
入力となつたことを条件として前記遮断した伝送
回線を自動復帰せしめる常閉スイツチと、前記符
号判定回路が正常符号受信を示す出力を発生して
いることを条件として伝送線からの受信符号を子
装置内へ取り入れるゲート回路とを設けたことを
特徴とする回線切離し装置。
1. In a code transmitting/receiving device in which a parent device and multiple child devices are cascade-connected via a transmission line with a defined transmission direction, it is determined whether the received code from the transmission line is in a predetermined format for each child device. a code determination circuit that determines the number of consecutive receptions of abnormal codes and the number of consecutive receptions of normal codes; The transmission line is cut off on the condition that the circuit continuously receives abnormal codes a predetermined number of times, and the transmission line is cut off on the condition that the circuit continuously receives normal codes a predetermined number of times or no received code is input within a certain period of time. A normally closed switch that automatically restores a cut-off transmission line, and a gate circuit that inputs the received code from the transmission line into the slave device on the condition that the code determination circuit generates an output indicating normal code reception is provided. A line disconnection device characterized by:
JP456679A 1979-01-17 1979-01-17 Line disconnection unit Granted JPS5596744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP456679A JPS5596744A (en) 1979-01-17 1979-01-17 Line disconnection unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP456679A JPS5596744A (en) 1979-01-17 1979-01-17 Line disconnection unit

Publications (2)

Publication Number Publication Date
JPS5596744A JPS5596744A (en) 1980-07-23
JPS6133418B2 true JPS6133418B2 (en) 1986-08-01

Family

ID=11587580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP456679A Granted JPS5596744A (en) 1979-01-17 1979-01-17 Line disconnection unit

Country Status (1)

Country Link
JP (1) JPS5596744A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714160B2 (en) * 1984-08-07 1995-02-15 株式会社東芝 Remote monitoring controller
JPH0758974B2 (en) * 1985-11-15 1995-06-21 株式会社東芝 Remote monitoring controller
JPS62179240A (en) * 1986-01-31 1987-08-06 Mitsubishi Cable Ind Ltd Automatic restoration method for circuit connection of converter for network
JP2722276B2 (en) * 1990-11-29 1998-03-04 株式会社日立テレコムテクノロジー Configuration control device for ring network

Also Published As

Publication number Publication date
JPS5596744A (en) 1980-07-23

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