GB1517925A - Storage field effect transistors - Google Patents

Storage field effect transistors

Info

Publication number
GB1517925A
GB1517925A GB36979/75A GB3697975A GB1517925A GB 1517925 A GB1517925 A GB 1517925A GB 36979/75 A GB36979/75 A GB 36979/75A GB 3697975 A GB3697975 A GB 3697975A GB 1517925 A GB1517925 A GB 1517925A
Authority
GB
United Kingdom
Prior art keywords
gate
drain
source
channel
floating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB36979/75A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19742445091 external-priority patent/DE2445091A1/en
Priority claimed from DE2505824A external-priority patent/DE2505824C3/en
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of GB1517925A publication Critical patent/GB1517925A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

1517925 Storage FETs SIEMENS AG 9 Sept 1975 [20 Sept 1974 12 Feb 1975] 36979/75 Heading H1K In an N-channel field effect transistor for the non-volatile storage of information comprising a floating insulated gate located over the channel between source and drain region formed in a substrate and a control gate capacitively coupled to it, and so constructed that it can be programmed by negatively charging the floating gate by channel electron injection the capacitance between the two gates is substantially, e.g. 5 times greater than that between the floating gate and the substrate, thereby allowing the use of lower operating voltages and reducing the influence of source and drain voltage on the floating gate. The desired capacitance ratio may be achieved by providing both gates with large overlapping extensions laterally of the channel or by disposing the control gate over such an extension of the floating gate. The transistor may be of the enhancement or depletion type. To facilitate programming the channel may be necked or underlie a thickened section of gate insulation adjacent the drain to provide an acceleration zone. The charge may be erased by irradiation with ultraviolet or X-rays, by avalanching of the source or drain junction or by channel injection. It is however preferred to erase using Fowler- Nordheim tunnelling and/or the gate surface effect. To allow the charge separation necessary for gate surface effect the floating gate should be at least 10,000 Š thick and consist of P-type polycrystalline silicon. Both effects are optimized at the expense of other mechanism involving greater heat dissipation, such as source or drain avalanching, by using silicon dioxide between 400 and 1200 Š thick as gate insulation, to so reduce heat dissipation that if desired all the transistors of an integrated matrix may be simultaneously erased without damage. The erasing voltage, direct for Fowler-Nordheim tunnelling and/or in the form of a train of steepfronted pulses or lower amplitude for gate surface effect, is supplied between the control gate and the source, drain or substrate region with the other regions preferably left floating and the control gate generally earthed. Undesirable contamination of the gate insulation can be reduced if the charging and erasing currents are arranged to pass through different parts of it, e.g. adjacent the source and drain respectively.
GB36979/75A 1974-09-20 1975-09-09 Storage field effect transistors Expired GB1517925A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19742445091 DE2445091A1 (en) 1974-09-20 1974-09-20 Storage FET with insulated storage gate - has insulated control gate and is fitted with high internal capacitance between gates
DE2505824A DE2505824C3 (en) 1975-02-12 1975-02-12 n-channel memory FET

Publications (1)

Publication Number Publication Date
GB1517925A true GB1517925A (en) 1978-07-19

Family

ID=25767730

Family Applications (1)

Application Number Title Priority Date Filing Date
GB36979/75A Expired GB1517925A (en) 1974-09-20 1975-09-09 Storage field effect transistors

Country Status (9)

Country Link
JP (1) JPS5157292A (en)
BE (1) BE833631A (en)
CH (1) CH601895A5 (en)
DK (1) DK422975A (en)
FR (1) FR2295523A1 (en)
GB (1) GB1517925A (en)
IT (1) IT1042648B (en)
NL (1) NL7510943A (en)
SE (1) SE415415B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2120454A (en) * 1982-03-09 1983-11-30 Rca Corp Nonvolatile floating gate memory device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4115914A (en) * 1976-03-26 1978-09-26 Hughes Aircraft Company Electrically erasable non-volatile semiconductor memory
JPS55105374A (en) * 1979-02-07 1980-08-12 Nec Corp Nonvolatile semiconductor memory
IT1201834B (en) * 1986-07-10 1989-02-02 Sgs Microelettronica Spa SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2120454A (en) * 1982-03-09 1983-11-30 Rca Corp Nonvolatile floating gate memory device

Also Published As

Publication number Publication date
DK422975A (en) 1976-03-21
FR2295523A1 (en) 1976-07-16
SE415415B (en) 1980-09-29
NL7510943A (en) 1976-03-23
JPS5157292A (en) 1976-05-19
IT1042648B (en) 1980-01-30
CH601895A5 (en) 1978-07-14
FR2295523B1 (en) 1981-10-09
SE7510484L (en) 1976-05-17
BE833631A (en) 1976-03-19

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
429A Application made for amendment of specification (sect. 29/1949)
429H Application (made) for amendment of specification now open to opposition (sect. 29/1949)
429D Case decided by the comptroller ** specification amended (sect. 29/1949)
SP Amendment (slips) printed
PCNP Patent ceased through non-payment of renewal fee