GB2120454A - Nonvolatile floating gate memory device - Google Patents

Abstract

A dual word line, electrically alterable, nonvolatile floating-gate memory cell has a word-line-to- floating gate capacitance (C3) which is significantly greater than either the program-line-to-floating gate capacitance (C2) or the floating-gate- to-substrate capacitance (C1). This allows the program line (46) and the word line (50) to be counter-driven to minimize coupling to the floating gate (42) during the write/erase cycle and to maximise coupling during the read cycle. The net result is higher write/erase/read efficiencies than heretofore possible. <IMAGE>

Description

SPECIFICATION Nonvolatile floating gate memory device This invention relates to a nonvolatile floating gate memory device.

The microprocessor-based system, as well as the related arts, have long required electrically alterable read only memory (EAROM) elements that were nonvolatile and many such devices have, to some extent, filled this need. However, as the computer arts have become more complex in nature and have required higher speeds and greater capacity, there now exists the need for a high-density memory device that may be easily programmed or "written" and, as the occasion arises, to reprogram ("erase" and "rewrite") the device in the field. To this end, devices are presently available to design engineers that exhibit nonvolatile characteristics but, as will be discussed, they have inherent shortcomings that are overcome by the subject invention.

One such device is found in the family of Floating Gate Avalanche Metal Oxide Semiconductor (FAMOS) devices. The advantage of this type of device resides in the fact that it is independent of any outside current to maintain the stored information in the event that power is lost or interrupted. Since this device is independent of any outside power, there is also no need to refresh the device, which feature results in a significant savings in power.

The floating gate family of devices usually has source and drain regions of a given conductivity type, formed in a substrate of the opposite conductivity type, at the surface thereof. Between the source and drain regions, and on the surface of the substrate, a gate structure is formed by first applying a thin insulating layer followed by a conductive layer (the floating gate) followed by a second insulating layer in order to completely surround the floating gate and insulate it from the remainder of the device. A second conductive layer (usually referred to the control gate) is formed over the second insulating layer (in the region of the floating gate) to complete the gate structure. Once such device is exemplified in U.S. Letters Patent 3,500,142 which issued to D. Kahng on March 1 0, 1970 and represents one of the early attempts to achieve nonvolatility.

The major drawback of the prior-art devices resides in the fact that high fields are required to produce the necessary avalanche breakdown in order for charge to be placed on the floating gate.

Further, to erase charge placed on the floating gate, some of the prior-art devices were provided with a transparent window so that they may be flooded with energy in the ultra violet or x-ray portion of the spectrum. Thus, it is extremely difficult to erase a single "word" without erasing all the charge on the device, then requiring that the entire device be completely reprogrammed. Further, the erasing step required an extremely long period of exposure time, of the order of about 30 to 45 minutes, with the device or chip removed from the equipment.

In recent years, the art has progressed to the point where nonvolatile, floating-gate read only memory devices have been produced which are electrically alterable. One such memory cell has been described in detail in an article entitled "1 6-K EE-PROM Relies on Tunneling for Byte-Erasable Program Storage" by W. S. Johnson, et al., ELECTRONICS, February 28, 1980, pp. 113-117. In this article, the authors describe a "Floating-Gate Tunnel Oxide" structure wherein a cell using a polycrystalline silicon (polysilicon) floating gate structure has its gate member charged with electrons (or holes) through a thin oxide layer positioned between the floating gate and the substrate by means of the Fowler-Nordheim tunneling mechanism. An elevation view of a typical device is described and shown in FIGURE 1 of the article.By using this type of structure, an excessively high floating gate-tosubstrate capacitance is produced. However, acceptable low-voltage "write" and "erase" operations can be achieved only when most of the applied voltage appears across the tunnel region which, in turn, requires that the floating gate-to-control gate capacitance be larger than the floating gate-to-substrate capacitance. Further, to achieve the required distribution of capacitance to produce the acceptable write and erase characteristics, the prior art has resorted to extending both the first and second polycrystalline silicon levels over the adjacent field oxide to obtain additional capacitance. The net results is an undesirably large cell.

In a patent application published in the United Kingdom as UK Patent Application GB 2,092,378A on 11 August 1 982, in the name of Xicor Inc. and entitled "Dense Nonvolatile Electrically-Alterable Memory Device with Substrate Coupling Electrode", the author describes a floating-gate nonvolatile memory fabricated with three layers of polycrystalline silicon. A fourth layer of polycrystalline silicon, embedded in the substrate surface, is used to bias the floating gate during the write, erase, and read operations. The mechanism for programming the device relys on asperities formed on the upper surface of the first polycrystralline silicon level (the programming electrode) to inject charge into the second polycrystalline silicon level (the floating gate).To erase the charge, asperities on the upper surface of the floating gate are used to induce charge to migrate from the floating gate to an overlying third polycrystalline silicon level which functions as the selec/erase electrode. The asperities, which texture the surface of the polycrystalline silicon layers, tend to intensify locally the electric fields, thereby lowering the effective polycrystalline silicon barrier height. However, this results in a compromise between read effectiveness and write/erase effectiveness. To merely alter the capacitance in order to improve the effectiveness of either the read operation or the write/erase operation, will tend to degrade the operation of the other.

According to the invention, there is provided a nonvolatile floating-gate memory device including semi-conductor material having a pair of regions of one conductivity type material formed therein and spaced from each other, with a region of another conductivity type material therebetween to define a channel region, a conductive floating gate insulated from the semiconductor material and having a portion thereof disposed over the channel region, a first conductive layer having a portion thereof disposed over and insulated from the floating gate and a second conductive layer disposed over and insulated from the first conductive layer, wherein the capacitive values between the floating gate, the first and second conductive layers and the semiconductor material have the relationship: C2 < C3 > C1 wherein:C, = the floating gate-to-material capacitance, C2 = the first conductive layer-to-floating gate capacitance; and C3 = the second conductive layer-to-floating gate capacitance.

An embodiment of the invention comprises a dual line, electrically alterable, nonvolatile floatinggate memory cell wherein the word- line-to-floating gate capacitance is made significantly greater than either the program-line-to-floating gate capacitance or the floating-gate-to-substrate capacitance, and by counter-driving each line (the program line and word line), the coupling to the floating gate is minimized during a write or erase cycle and maximized during the read cycle, thereby providing a cell having higher write/erase/read efficiencies than heretofore possible.

In the drawing: FIGURE 1 is a schematic representation of the prior-art floating-gate memory device illustrating the capacitive distribution with respect to the control gate, floating gate and substrate; FIGURE 2 is a schematic representation of the floating-gate memory device of the present invention, illustrating the capacitive distribution achieved therein; FIGURE 3 is a plan view of a floating-gate memory device made in accordance with the teaching of the present invention; FIGURE 3A is a cross-sectional view of the device of FIGURE 3 taken along line A-A of FIGURE 3; and FIGURE 3B is a cross-sectional view of the device of FIGURE 3 taken along line B-B of FIGURE 3.

FIGURE 1 shows a schematic representation of a prior-art floating-gate device wherein asperities on the upper surface of a polycrystalline silicon floating-gate are used to intensify the electric fields in order to lower the effective barrier height This prior-art device is formed in a substrate 10 of a first conductivity type, the substrate 10 being provided with a layer 12 of field oxide on the top surface thereof to define the active areas and to insulate one cell from another. The active areas consist of source and drain regions 14 and 16, respectively, which regions are formed of a conductivity type opposite of that of the substrate 1 0. These regions may be formed either by ion implantation or by difussion.An intermediate region 18 is thus provided between source and drain regions 14 and 16 and, as is well known in the art, is made to support conduction by an inversion layer at the surface of substrate 10. A gate oxide layer 20 is provided as an insulator for floating gate 22, which is usually a doped polycrystalline silicon layer. Similarly, an inter-polycrystalline silicon insulating oxide layer 24 is provided in order to insulate polycrystalline silicon layer 26 from polycrystalline silicon layer 22. As is well known in the art, polycrystalline silicon layer 26 is usually referred to as the control gate, while polycrystalline silicon layer 22 is identified as the floating gate.

Since the polycrystalline silicon layers 22 and 26 are conductive layers that are separated by the insulating layer 24, the capacitance resulting from the cooperation of these three elements may be determined by the areas of overlap of the layers, and the thickness and quality of insulating oxide layer 24. The is represented by C2. Similarly, the capacitance formed by the cooperation of polycrystalline silicon layer 22, oxide layer 20 and substrate 10 is shown as C,. In the conventional planar polycrystalline silicon injector cells, the capacitive coupling elements C, and C2 are about equal.When a potential of about 20 volts is applied between polycrystalline silicon layer 26 and substrate 10 (to write or erase charge on the floating gate 22), the 20 volts will be divided eually with about 10 volts appearing across inter-polycrystalline silicon oxide layer 24 (C2), where it contributes to tunneling, while the remaining 10 volts appearing across the gate oxide layer 20 (C,), where it is effectively wasted.

During the read cycle, the situation is reversed in that, when a 5 volt read signal is applied, half of the voltage will occur across inter-polycrystalline silicon oxide layer 24 (C2). Thus, only the 2 1/2 volt potential appearing across the gate oxide 20 (C,) serves to control the channel region 38. Since C,=C2, the efficiency may be expressed as follows: C, read efficiency = =50% = 50% (1) C, + C2 C2 erase/write efficiency = ------- = 50% (2) C, + C2 GB 2 120 454 A It should be obvious now that, if the capacitive distribution is altered to improve either the read efficiency or the erase/write efficiency, such improvement in one operation will degrade performance in the other operation.

FIGURE 2 shows, schematically, the floating-gate memory device of the present invention where both higher read efficiency and higher erase/write efficiencies are achieved using the dual lines (word and program) herein shown. In the present device, a substrate 32 of a first conductivity type is provided with source and drain regions 34 and 36, respectively, together with an intermediate channel region 38 for supporting conduction. Field oxide layer 33 serves to define the active regions and to separte and insulate one cell from another. Gate oxide layer 40 is provided on the surface of the substrate 32 over the channel region 38, and has a thickness of about 500 angstroms and serves to insulate polycrystalline silicon layer (floating gate) 42 from the substrate 32. The resultant capacitance is herein designated as C,.Polycrystalline silicon layer (program line) 46 is insulated from the floating gate 42 by inter-polycrystalline silicon oxide layer 44 which may have a thickness of about 200 angstroms. The resultant capacitance is herein designated as C2. Polycrystalline silicon layer 46 is insulated from polycrystalline silicon layer (word line) 50 by oxide layer 48 which may have a thickness of about 500 angstroms, and the capacitance between the polycrystalline silicon layers 42 and 50 is herein designated as C3.

As will be seen in subsequent FIGURES, the dimensions of the polycrystalline silicon layers 50, 42 and 46 have been tailored in order to meet the following conditions: C3=C2=C, (3) (3) and C2 < C3 > C1 (4) (4) wherex > 1:y > 1.

Further, when performing the write or erase functions, the polycrystalline silicon layers 46 and 50 are counter-driven to maximize the electric field between polycrystalline silicon layer 46 and polycrystalline silicon layer 42 (across oxide layer 44). During the read operation, the polycrystalline silicon layer 46 and 50 are driven together (the same voltage of the same polarity applied thereto), in order to maximize the electric field across the gate oxide layer 40.

The following table shows the nominal potentials that may be applied to each of the elements of the present device in order to perform the erase, write and read functions. In the table, the various potentials shown in each of the columns are applied to the elements shown in the column entitled "ELEMENT'.

ELEMENT WRITE ERASE READ Source 34/Drain 36/and Substrate 32 O/O/Ov 20/20/20v 0/2.5/Ov Poly Line 46 20v Ov 5v Poly Line 50 Ov 20v 5v Thus, in the cell shown in FIGURE 2 where, by way of example, x and y equal 3, then: (5) C3=3C2=3C1 (5) (5) The efficiencies may then be expressed as follows: C2+C3 write efficiency = --------- = 80% (6) C1 + C2 + C3 The erase efficiency will be similar to the above write efficiency (6) except, as shown in the above table, the voltage applied to the polycrystalline silicon layers 46 and 50 are reversed. With the capacitance ration shown, the erase efficiency should be about equal to the write efficiency.Thus, with 20 volts applied to the cell of the subject application, a total of about 16 volts is available for writing and erasing the cell, instead of only 10 volts that was available in the prior art.

During the read operation, as shown in the table, the polycrystalline silicon lines 46 and 50 have 5 volts applied thereto, and 2.5 volts is applied to the drain 36. Under these circumstances wherein the polycrystalline silicon lines 46 and 50 have 5 volts applied thereto, the lines 46 and 50 are driven together in order to maximize the field appearing across the oxide layer 40. The read efficiency may now be expressed as follows: C1+C3 read efficiency = --------~- = 80% (7) C1 + C2 +C3 The net result of this higher read efficiency is to provide a 4 volt signal for decoding the channel region 38, instead of the 2.5 volts available in the prior art.

Accordingly, by tailoring the various capacitances, we are able to effectively alter the capacitive distribution ratio in order to make it higher for both the read operation and the write/erase operations than possible with the prior art. Both read and write/erase operations are then faster, safer, and more efficient. Also, when the polycrystalline silicon layers 46 and 50 are driven together (the same voltage of the same polarity applied thereto), the potential induced across tunneling oxide layer 44 is reduced to only 1 volt during the read operation. The increase in the capacitive distribution ratio reduces greatly the likelihood of any smearing along unselected word lines during a write/erase operation, and further reduces the likelihood of disturbing adjacent cells during a read operation.

FIGURES 3, 3A, and 3B show a P type substrate 32 with parallel N type doped lines 34 and 36 representing the source and drain regions, respectively. The source and drain regions 34 and 36 are separated by channel region 38 which is made to support conduction by an inversion layer, as is well known in the art. The active region, consisting of source and drain regions 34 and 36, respectively, and channel regions 38 is defined by field oxide layer 33 which is formed on the top surface of the substrate 32. While the active region is shown as having been formed in a P type substrate, those skilled in the art will readily recognize that the P type region designated as 32 may also be a P type well formed in an N type substrate.

A gate oxide layer 40 having a thickness of about 500 angstroms is formed over both the active region and the field oxide layer 33. A doped polycrystalline silicon layer is then formed on the oxide layer 40, masked and defined to form an "hour-glass" shaped floating gate 42 wherein the narrow portion of the "hour-glass" is aligned with the channel region 38, in order to tailor the floating gate-to-substrate capabitance. The capacitance formed between the floating gate 42 and the substrate 32 is equivalent to C1 in FIGURE 2. While we have chosen to tailor the floating gate 42 so as to have an hour-glass configuration, we do not wish to be so limited. Any other shape will suffice provided the criteria of equations (3) and (4) are met.

A second oxide layer 44 having a thickness of about 200 angstroms is then formed over the floating gate 42 as well as over the gate oxide layer 40 and the field oxide layer 33. Thereafter, another doped polycrystalline silicon layer is deposited, masked and defined to form program line 46 which runs in a direction generally perpendicular to the floating gate 42. The combination of the overlap of the program line 46 over the floating gate 42 together with the oxide layer 44 constitutes capacitance C2.

Program line 46 is then provided with an oxide layer 48 which is deposited over the entire structure to a thickness of about 500 angstroms, followed by the deposition of a doped layer which is masked and defined to form word line 50. Word line 50 has its outer edges aligned with the ends of floating gate 42 in order to maximize the word-line-to-floating gate capacitance. The resultant capacitance is herein designated as C3.

Although it has not been shown, those skilled in the art will recognize that source line 34, drain line 36, polycrystalline silicon (program) line 46 and polycrystalline silicon (word) line 50 all terminate in insulated pads (not shown) at the edges of substrate 32 in order to provide the appropriate signals to write, erase and read the cell. Further, a protective passivating layer may be applied over polycrystalline silicon layer 50 in order to protect it from the atmosphere.

Additionally, while we have shown and described the present device as being formed in bulk silicon, those skilled in the art will readily recognize that the cell described may be fabricated on an insulative substrate such as sapphire, spine or monocrystalline beryllium oxide.

While the operation of a single device has been described, it should be obvious to those skilled in the art that a plurality of these devices may be assembled in rows and columns to form an array. Such an array may be arranged in a single well. The common source and drain lines (34 and 36) would be shared by all the devices in one column, while the remaining columns in the well would have their respective sources and drains similarly shared. Program line 46 and word line 50 would be common to each device in corresponding rows in each column. Thus, to form a 1024-bit array, one would form 32 columns of shared sources and drains with 32 devices in each row connected to program an word lines.

However, each device would have its own floating gate member 42. Accordingly, by appropriately biasing the source and drain lines 34 and 36 as well as substrate 32, as shown in the table, one could very easily "write", "erase" or "read" any one of the 1024 devices present.

While the present device has been described in terms of multiple layers of polycrystalline silicon, we do not wish to be so limited. It should now be obvious to those skilled in the art that various other conductive layers formed of refractory metals, refractory metal silicides, etc., or any combination thereof, may be used in place of the polycrystalline silicon layers 46 and 50.

Claims (10)

1. A nonvolatile floating-gate memory device including semi-conductor material having a pair of regions of one conductivity type material formed therein and spaced from each other, with a region of another conductivity type material therebetween to define a channel region, a conductive floating gate insulated from the semiconductor material and having a portion thereof disposed over the channel region, a first conductive layer having a portion thereof disposed over and insulated from the floating gate and a second conductive layer disposed over and insulated from the first conductive layer, wherein the capacitive values between the floating gate, the first and second conductive layers and the semiconductor material have the relationship: C2 < C3 > Ca wherein:: Cr = the floating gate-to-material capacitance, C2 = the first conductive layer-to-floating gate capacitance; and C3 = the second conductive layer-to-floating gate capacitance.

2. The floating-gate memory device of claim 1 wherein: the conductive floating gate and the first and second conductive layers are selected from the group consisting of doped polycrystalline silicon, refractory metals and refractory metal silicides.

3. The floating-gate memory device of claim 2 wherein: the source and drain regions are parallel lines with the channel region lying between portions of the doped parallel lines; a portion of the floating gate is aligned with the channel region and oriented in a direction parallel to the source and drain lines; the first and second conductive layers are polycrystalline silicon lines disposed parallel to each other over the channel region and disposed perpendicularly with respect to the orientation of the floating gate, and the ends of the floating gate are aligned with the lengthwise edges of the second polycrystalline silicon line.

4. The floating-gate memory device of claim 3 wherein: the floating gate is insulated from the channel region by a layer of silicon oxide having a thickness of about 500 angstroms; the first polycrystalline silicon layer is a program line insulated from the floating gate by a layer of silicon oxide having a thickness of about 200 angstroms; and the second polycrystalline silicon line is a word line insulated from the first polycrystalline silicon layer by a layer of silicon oxide having a thickness of about 500 angstroms.

5. The floating-gate memory device of claim 1, 2, 3 or 4 wherein: the channel region of the semiconductor material is doped with P type conductivity modifiers; and the source and drain regions are doped with N type conductivity modifiers.

6. The floating-gate memory device of claim 1, 2, 3, 4 or 5 wherein: the floating gate is "hour-glass" shaped with the narrow portion thereof aligned with the channel region.

7. The device of claim 1, 2, 3, 4, 5 or 6 wherein the said semiconductor material is part of a substrate of semiconductor material.

8. The device of Claim 1, 2, 3, 4 5 or 6 wherein the said semiconductor material is on an insulative substrate.

9. A floating-gate memory device substantially as described hereinbefore with reference to FIGURES 2 and 3, 3A and 3B of the accompanying drawings.

10. A memory system comprising a device according to any preceding claim and means for applying: a reference potential to the semiconductor material and the second layer and a first potential to the first layer to perform a write operation; the reference potential to the first layer, and the first potential to the semiconductor material and the second layer to perform an erase operation; and a second potential intermediate the reference and first potential to the first and second layers a third potential intermediate the reference and second potentials to one of the pair of regions of one conductivity type material and the reference potential to other regions of the semiconductor material to perform a read operation.