GB1509458A - Electronic circuit in a quartz crystal watch - Google Patents

Abstract

1509458 Electronic timepieces EBAUCHES S A 1 Aug 1975 [30 Aug 1974] 32209/75 Heading G3T In an electronic timepiece comprising a crystal controlled oscillator circuit 1, Fig. 1, followed by a frequency divider 4, control logic circuit 5 and driver circuit 6 driving a stepping motor 7, a signal f 1 from an early stage in the divider, e.g. output 8, is conducted to a terminal B of the motor to provide a test point for checking the oscillator frequency. In addition this measurement signal goes from terminal A of the motor (the motor resistance bing relatively low) to a comparator 9 which compares it with a "reading signal" from divider output 10 or derived from the conjunction of several output pulse trains f 1 , f 2 , f 3 from the Q outputs of the divider flip-flops i, j, k in Fig. 2. The comparator detects the presence or absence of the measurement frequency signal at A between drive pulses to the motor. When a switch 11 is open the measurement signal passes from B to A and the comparator produces no reset pulses to the divider. However with switch 11 closed, terminal A is at the potential + V BB and the low internal resistance of the battery short circuits the measurement signal. Consequently comparator 9 resets at least the last stage of divider to zero and locks it/them in that state. Thereby the watch is stopped and the time display can be set. In Fig. 2, the frequency divider comprises stages a to w, the input f O to which is at 32768 Hz. The output of stage o is at 1 Hz. Stages p to s and a corrector 18 divide this frequency by ten; stages t to v divide the result by six so that the output period of stage v is one minute. The Q and Q outputs of stage w alternately open NAND gates 20, 21 each minute. The Q output of stage v permits one pulse/min of the Q output of stage j to reach NAND gates 20, 21. The pulse to arrive at the NAND gate which has just opened will be passed via a respective one of inverters I 1 , I 2 to control a transistor bridge T 1 to T 4 whereby to pass drive current pulses in opposite directions alternately through the motor winding 7. To prevent short-circuiting of the battery if switch 11 is closed when transistor T 1 is conducting, a circuit including transistors T 5 to T 9 is provided such that T9 is driven to saturation and blocks T 1 . The pulse train f 1 from the Q output of stage k is used as the signal to be measured at terminal A or B and is applied to NAND gate 14 (comparator 9 of Fig. 1) together with the "reading" signal which is derived from the conjunction of f 1 , f 2 , f 3 , Fig. 3, (not shown) in NAND gate 12 after inversion in inverter 13. The output of gate 14 is a reset pulse train RES which after inversion at 15 functions to reset stages l, m, n, o to zero and which is applied to gates 16, 17 the outputs of which reset stages p to s and stages t to v respectively. In an alternative embodiment, Fig. 4, (not shown) the motor drive pulse circuit comprises MOS transistors.