GB1492925A - Synchronising receiver clock circuit - Google Patents

Abstract

1492925 Data transmission; synchronizing POST OFFICE 25 Nov 1974 [23 Aug 1973] 40051/73 Heading H4P An arrangement for synchronizing a receiver clock with randomly occurring incoming data transitions comprises an oscillator including an inverting Schmitt trigger stage tuned to bit rate frequency having phase resetting means responsive to transitions which resets the oscillator to a determined phase relation, the oscillator being sufficiently stable to bridge the longest gap which can occur. The phase resetting means may include a monostable operable in response to "1" bits. Oscillator I may be an integrated Schmitt trigger circuit feedback tuned by a variable capacitor 9 and monostable 5 may also be an integrated circuit with its time constant settable by variable capacitor 11, its output being inverted by gate 7 through which through diode 4 shunts capacitor 9 hence inhibits oscillator 1 i.e. on each "1" leading transition oscillation of oscillator 1 is inhibited for the set time of monostable 5. In a refined arrangement (Fig. 3, not shown) inverter and AND gate (12, 13) are included to prevent spurious noise signals inhibiting the oscillator for any significant time. Both the above arrangements can be used with duty cycles up to 100% for 1 bits. An alternative arrangement is given in Fig. 4 (not shown) for a 50% duty cycle which comprises an oscillating inverting feedback amplifier (19) tuned by a variable capacitor with data pulses fed through an inverting amplifier (15) and diode (4).