GB1491524A - Method and apparatus for processing data - Google Patents
Method and apparatus for processing dataInfo
- Publication number
- GB1491524A GB1491524A GB600775A GB600775A GB1491524A GB 1491524 A GB1491524 A GB 1491524A GB 600775 A GB600775 A GB 600775A GB 600775 A GB600775 A GB 600775A GB 1491524 A GB1491524 A GB 1491524A
- Authority
- GB
- United Kingdom
- Prior art keywords
- main memory
- maintenance panel
- memory
- programme
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Programmable Controllers (AREA)
- Electric Clocks (AREA)
- Slot Machines And Peripheral Devices (AREA)
Abstract
1491524 Programme interruption COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII HONEYWELL BULL 12 Feb 1975 [13 Feb 1974] 6007/75 Heading G4A When the execution of a programme stored in an area P of a main memory 10 of a dataprocessing unit is interrupted, the contents of registers used by the programme and data stored in the main memory 10 are transferred to a reserved area of a memory, the data transferred to the reserved area being able to be examined and/or altered if necessary by an operator by means of a control unit 30, the data in the reserved area then being retransferred to main memory 10, with all of these steps being controlled by microprogrammes. In the illustrated embodiment, these microprogrammes are stored in an area p of the main memory 10, and the reserved area is located in an auxiliary memory 20, but the microprogrammes may alternatively be stored in an auxiliary memory, and the reserved area may be located in the main memory 10. The control unit 30 incorporates a maintenance panel on which the address of a desired data item may be set, this address being checked in a comparator 31 to determine whether it is less than the maximum address limits of main memory 10 and auxiliary memory 20; if this is so the value of the data item read from memory (10 or 20) or the value of the data item written into memory is displayed on the maintenance panel. The interrupted or "stopped" state is initiated at the end of execution of a programme instruction when a "stop" order is present at the control unit 30. A rotary switch on the maintenance panel determines which one of three modes of initiation of the "stopped" state shall be employed, each resulting in the generation of a "stop" order at the control unit 30: (1) initiation by actuation of a "stop" button on the maintenance panel; (2) initiation following the execution of each instruction, or (3) initiation following the execution of an instruction whose address is set on the maintenance panel. A further rotary switch on the maintenance panel determines the operation to be performed on the selected data item, viz. read or write from or into the main memory 10 or a register. Following any desired examination or alteration of the data item, actuation of a "resume" button on the maintenance panel causes retransfer of the data to their initial addresses in main memory 10 or in the registers, the programme resuming execution at a point determined by the stored value of an instruction counter. Should resumption of the programme be attempted in mode (3) of initiation of the "stopped" state, i.e. with an address set on the maintenance panel, this is prevented unless the set address is valid, i.e. unless it is less than the maximum address limits of the memories.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7404893A FR2260829B1 (en) | 1974-02-13 | 1974-02-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1491524A true GB1491524A (en) | 1977-11-09 |
Family
ID=9134867
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB600775A Expired GB1491524A (en) | 1974-02-13 | 1975-02-12 | Method and apparatus for processing data |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR2260829B1 (en) |
GB (1) | GB1491524A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IN155448B (en) * | 1980-03-19 | 1985-02-02 | Int Computers Ltd |
-
1974
- 1974-02-13 FR FR7404893A patent/FR2260829B1/fr not_active Expired
-
1975
- 1975-02-12 GB GB600775A patent/GB1491524A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2260829A1 (en) | 1975-09-05 |
FR2260829B1 (en) | 1977-09-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |