GB1485372A - Electrical apparatus for the production of pulses - Google Patents

Abstract

1485372 Electrical muscle exercisers SLIM MASTER BEAUTY EQUIPMENT (SALES) Ltd 27 Nov 1974 [4 Oct 1973] 46514/73 Heading A5R [Also in Divisions H3 and H5] A pulse circuit more particularly for an electrical muscle exerciser comprises a pulse generator G, Fig. 1A, means for feeding the pulses to an output in controlled periods and means for varying the intervals between the periods by a generator having an output cycle comprising at least four states. The pulse generator G comprises a unijunction transistor oscillator, an amplifying transistor T6 and a NAND gate GL4 arranged as an inverter. Pulse frequency is controllable by VR1. The output of GL4 provides an input to a NAND gate GL3b and also acts as a clock input to a flip-flop SL2a arranged to produce at outputs Q, Q two square waves in anti-phase with 1:1 mark/space ratio, provided that switch S1 is open. The Q, Q outputs are applied to NAND gates GL3a, GL3b respectively, arranged to provide an output in the presence of a logic 1 signal from a monostable circuit MONO 1 (ML1) cross coupled with a second monostable circuit MONO 2 (ML 5) to provide a second oscillator, Fig. 1c. The pulse outputs pass alternately via transistors T1, T10 or T2, T11 to the primaries of ten parallel-connected transformers, Fig. 1B, the secondaries of which are connected to muscle treatment contact pads via pulse amplitude controls Pt2 &c. The pulses due to T10 and T11 are of. opposite polarity. If switch S1 is closed the Q output is fixed at logic O and pulses are only passed by. T11. A Miller integrator M, Fig. 1B, also' initiated from MONO 1, by a logic O signal, is arranged to turn on slowly a transistor T3, thus providing a slow increase of pulse amplitude at the start of each period, Fig. 7 (not shown). The duration of a pulse period is determined by the time constant of a capacitor C4, connected to MONO 1, Fig. 1C, in combination with resistors R7, VR2. At the end of the pulse period the complement of the output of MONO 1 triggers the other monostable circuit MONO 2. The time interval before the next pulse period is determined by C5, R8, VR3, and also R11 if a transistor T7 is off. T7 may be turned on by setting a switch S2 to the 'CONSTANT' position; if however switch S2 is set to either the 'MODE 1' or the 'MODE 2' position the moment when T7 isturned on is controlled by a pseudo-random generator RG, Fig. 1D. Thus in the latter positions of S2 the interval between pulse periods is increased by an amount determined by the output cycle of RG. Generator RG comprises bistable units SL2b, SL6a, SL6b, with NAND gates GL7a, GL7b and GL7d forming a non-equivalence circuit which outputs to MODE 1 a zero when the outputs of SL2b and SL6b are equivalent, Fig. 6 (not shown). A NAND gate GL7c connected as an inverter provides the complementary output to switch position MODE 2. A NAND gate GL3c is used to prevent the generator from 'locking up' if the real outputs of the three bistable units are all zero.