GB1482603A - Data processing system - Google Patents

Abstract

1482603 Data processing systems DATA GENERAL CORP 25 July 1974 [10 Aug 1973] 32971/74 Heading G4A The central processor unit of a data processing system includes a register file 30 (Fig. 2) having two write ports 1W, 2W and two read ports 1R, 2R, the latter being connected as the inputs to an arithmetic and logic unit 31, the output from which is connected to one of the write ports 2W, one of the read ports 2R being coupled to the other write port 1W. A timing generator controls the timing operation of the CPU. The system also includes a memory unit having a timing generator, a master clock generating a reference time base so that the timing signals for the memory and central processing unit are out of phase. The central processing unit is the control unit for the system and governs all input/ output equipment, performs all arithmetic/logic operations and sequences the programmes. The register file 30 includes four accumulator registers a program counter register, a memory register and two temporary registers reading from and writing into the same register being possible since write occurs at the edge of a clock pulse. The two read ports enable for example the source accumulator and the destination accumulator to be accessed in a dual operand arithmetic operation and eliminate the need for multiplexer units at the output. The first write port is also connected via a multiplexer 35 to the data memory bus 14 which is linked to memories and IO devices. Preferably the register file comprises eight integrated circuits (250-257, Fig. 2A, not shown) feeding four ALU integrated circuits (258-261, Fig. 2B, not shown) each handling four bits. A shift network 33 connected to the output of the unit 31 comprises eight integrated circuit units (262-269, Fig. 2C, not shown) each handling two bits, there being an additional zero carry unit (270). The system operates in one of a plurality of programming operating states, the states being divided into three groups, "fetch/defer", "MR1- execute" and "arithmetic/I.O. execute". The first group includes states for instruction movement, address movement and programme interrupt. The second group (memory reference instruction) includes states for programme sequence alteration, i.e. jump. The third group includes arithmetic calculations and data movement to and from peripherals. Read only memory units provide the necessary signals for operation in these states. The basic timing unit for the central processor includes a register (160, Fig. 12, not shown) controlled from an oscillator (161) the basic clock signal (CPU, CLK) at the output of the unit being extendable by logic circuitry (164). Further logic circuitry (167) is used for temporarily halting the CPU. The timing logic utilized in the memory unit to control write, read, inhibit and strobe is controlled by the inverse of the oscillator signal to maintain the desired predetermined phase relationship between the CPU and memory timing systems.