GB1479404A - Data processing apparatus - Google Patents

Data processing apparatus

Info

Publication number
GB1479404A
GB1479404A GB576375A GB576375A GB1479404A GB 1479404 A GB1479404 A GB 1479404A GB 576375 A GB576375 A GB 576375A GB 576375 A GB576375 A GB 576375A GB 1479404 A GB1479404 A GB 1479404A
Authority
GB
United Kingdom
Prior art keywords
vector
operands
order
buffer
operand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB576375A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Control Data Corp
Original Assignee
Control Data Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US450632A external-priority patent/US3898626A/en
Priority claimed from US470896A external-priority patent/US3919534A/en
Application filed by Control Data Corp filed Critical Control Data Corp
Publication of GB1479404A publication Critical patent/GB1479404A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
GB576375A 1974-03-13 1975-02-11 Data processing apparatus Expired GB1479404A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US450632A US3898626A (en) 1974-03-13 1974-03-13 Data processing apparatus
US470896A US3919534A (en) 1974-05-17 1974-05-17 Data processing system

Publications (1)

Publication Number Publication Date
GB1479404A true GB1479404A (en) 1977-07-13

Family

ID=27036074

Family Applications (1)

Application Number Title Priority Date Filing Date
GB576375A Expired GB1479404A (en) 1974-03-13 1975-02-11 Data processing apparatus

Country Status (5)

Country Link
JP (1) JPS599944B2 (enExample)
DE (1) DE2505518A1 (enExample)
FR (1) FR2264323B1 (enExample)
GB (1) GB1479404A (enExample)
NL (2) NL181055C (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2476800A (en) * 2010-01-07 2011-07-13 Linear Algebra Technologies Ltd Sparse matrix vector multiplier using a bit map of non-zero elements to control scheduling of arithmetic operations

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5933554A (ja) * 1982-08-18 1984-02-23 Nec Corp オペランド供給装置
US5689653A (en) * 1995-02-06 1997-11-18 Hewlett-Packard Company Vector memory operations

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735360A (en) * 1971-08-25 1973-05-22 Ibm High speed buffer operation in a multi-processing system
JPS5223704B2 (enExample) * 1971-09-02 1977-06-25
JPS5728219Y2 (enExample) * 1973-12-26 1982-06-19

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2476800A (en) * 2010-01-07 2011-07-13 Linear Algebra Technologies Ltd Sparse matrix vector multiplier using a bit map of non-zero elements to control scheduling of arithmetic operations
WO2011083152A1 (en) 2010-01-07 2011-07-14 Linear Algebra Technologies Limited Hardware for performing arithmetic operations

Also Published As

Publication number Publication date
AU7854475A (en) 1976-08-26
NL181055B (nl) 1987-01-02
NL7502309A (nl) 1975-09-16
FR2264323B1 (enExample) 1980-05-30
NL181055C (nl) 1987-06-01
FR2264323A1 (enExample) 1975-10-10
DE2505518A1 (de) 1975-09-18
JPS599944B2 (ja) 1984-03-06
JPS50123242A (enExample) 1975-09-27
DE2505518C2 (enExample) 1990-03-01
NL8602882A (nl) 1987-03-02

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee