GB1479404A - Data processing apparatus - Google Patents

Abstract

1479404 Vector processing CONTROL DATA CORP 11 Feb 1975 [13 March 1974 17 May 1974] 5763/75 Heading G4A Individual streams of operands A 1 -A n and B 1 -B m forming a respective operand vectors A, B are passed through a buffer system in order to align the operands of one stream with correspondingly positioned operands in the other stream. The operands are supplied from a memory which is divided into banks a plurality of which may be accessed simultaneously, and misalignment of operand pairs arises, in part, because, once accessed, a bank cannot be accessed again for a given period (called a major cycle). When any bank is shared by two vectors or two banks share the same addressing circuits an accessing conflict may result. The first accessed operands of a vector, e.g. vector A, are temporarily stored in buffer registers 28, 26 and 17, Fig. 2, which are filled in that order, and then, if necessary in a buffer store 38 until the first accessed operand of the other vector B appears at the output of the corresponding buffer register 33. Thereafter, pairs of operands are read out of the buffer registers 28, 33 with new operands passing straight to buffer registers 31, 33 in the case of the vector B and via buffer register 17 or buffer store 38 to buffer registers 26, in the case of vector A. Resultants forming a resultant vector and derived by an arithmetic operation performed on operand pairs A 1 B 1 , A 2 B 2 and so on are buffered at 61 until the required memory bank(s) is(are) free (line 54). A counter 62 signals control 44 to store operands and thus halt the generation of further resultants when a given number of resultants have been stored in buffer 61. In order to save storage space, only non-zero and finite operands may be stored, and in this case, each such sparse operand vector has an associated order vector the 1 and 0 bits of which indicate the presence and absence of correspondingly ordered operands in the memory. The order vectors X, Y for two operand vectors A, B are read from memory to corresponding buffer registers 112, 115, Fig. 5, and thereafter are examined bit by bit in channels 116-120 and 121-125 to enable an output from operand registers 104, 109 only when the current order vector bit is a 1. Additional logic 126-128 causes shifting of the partial order vectors (up to 16 bits) in registers 117, 122 to skip positions in which both order vectors have 0 bits. Circuits are also described for generating the order vector Z for a resultant vector and for controlling the storage of resultants to derive a sparse resultant vector.