GB1472464A - Digital signal generator for testing the reception side of a pcm multiplex terminal - Google Patents

Abstract

1472464 Testing PCM multiplex terminals WANDEL u GOLTERMANN 10 April 1974 [25 April 1973] 15848/74 Heading H4M A digital signal generator for testing the decoder and demultiplexer at a terminal station in a P.C.M., T.D.M. communication system provides frame synchronizing and signalling words for frames of a P.C.M. test signal, together with a selectable sequence of P.C.M. code words representing a sine wave of predetermined frequency and amplitude, and a further P.C.M. word. The selectable sequence is applied to a desired information channel of the test signal frame and the further word is applied to the remaining channels for application to the input of the terminal station. This enables crosstalk to be measured, in addition to checking the decoding, frequency response &c., by measuring the analogue outputs in the remaining channels at the terminal station. Level dependence may be measured by selecting a P.C.M. sequence representing sinewaves of the same frequency but different amplitudes. Other measurements may be carried out by selecting a P.C.M. sequence representing different frequencies of the same amplitude. To check the correct recognition and transfer of operational signalling the generator may be arranged to produce test words in the signalling channel 0 of alternate frames, alternating with the frame sync signal. The triggering of a framing fault alarm may be tested by arranging that in the P.C.M. frame successive frame sync words are interfered with and provision may also be made for checking a superframe framing error alarm in this manner. The generator may provide a signal at a separate output terminal dependent on the selected code sequence for use with an oscilloscope and may also provide a clock signal at a further separate output terminal. A code converter may be provided to allow testing of terminal equipment with different coding arrangements. The generator incorporates an internal clock 1 which times operation of the frame control circuit 7 and parallel-serial converter 5 and produces an output at 6. The control circuit 7 incorporates a number of coincidence circuits and a number of frequency dividers, so that channels, frames and superframes may be defined relative to the bit rate from the clock. The control circuit outputs actuate stores 8-12, which contain respectively in 8 a frame synchronizing word, in 9 a test word for the signalling channels 0, in 10 the "further word" to be applied to unoccupied channels, in 11 a superframe sync word and in 12 a fill word, simulating signalling to be applied to channel 16 in frames 1-15. The sequence of P.C.M. words to be applied to the channel to be tested in read out from a store 18 using control signals provided by control circuitry 19. The words from the various stores are applied at appropriate times to the parallel serial converter 5 and hence via code converter 15 to the generator output. The control 19 enables the particular frequencies or amplitudes of the P.C.M. sequence to be adjusted, and the particular channel to be investigated is selectable by an adjustment of the control 7.