GB1459450A - Computer configuration - Google Patents

Abstract

1459450 Accessing stores PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES 31 Dec 1973 [8 Jan 1973] 60309/73 Heading G4A Processors A, B (Fig. 2, not shown) access, via a switching unit, storage banks 0, 1 during an eight pulse clock cycle, the arrangement being such that access for reading is permitted during the modification part of an access for reading, modifying, and writing. Locations SBO1, SBO2; SB11, SB12 in the banks are reserved for indicating activity status i.e. when associated storage locations are being accessed for modification. When a process operating on one of the processors A, B requests access to one of the banks 0, 1 a bi-stable associated with the process, e.g. for process 2 in processor A bi-stable PROF(2) (Fig. 4), is set and if a read access is required a bi-stable R(2) is also set. A further bi-stable MRQF(2) is then set at clock pulse 0 to control bi-stable MRQFA to generate a memory request signal MEMREQA for processor A. A priority unit PR1 determines the priority between competing processes of the same processor, two bi-stable elements MSPSA holding the number, in this case 2, of a successful process. The address is entered into register ADREG(2) and for a write operation the data is held in DATAREG(2). The most significant bit A0 of the address indicates whether access is required to bank 0 or bank 1 so that one of a pair of AND gates AND1, AND2 (Fig. 5) is enabled. If processor B is competing for the same bank the corresponding gate of a second pair of AND gates AND3, AND4 is enabled, a priority unit PR4 (for bank 0) and PR5 (for bank 1) then determining which processor is to be granted access, bi-stable elements SPF0, SPF1 being set to the relevant state at clock pulse 2. At clock pulse 3 bi-stables BRQF0, BRQF1 are set if access to their blocks is requested to generate signals REQ0, REQ 1 respectively. The switch unit is advanced by clock pulses 4, 5 and at clock pulse 6 bi-stable MOKFA is set to indicate that processor A has been granted access. At clock pulse 6 of the next cycle if a read access is requested the data is read into the data register DATAREG(2) and at clock pulse 7 bi-stable PROF(2) is reset. When a processor wishes to make a claim access i.e. one for reading, modifying and writing, a bi-stable CF (Fig. 4) is additionally set so that, for example for process 2 requesting block 0, bi-stables CLSPFAO are set to the number 2 via AND gate 9 and priority unit PR2. At the next clock pulse bi-stable CLRQSAO is set to generate a claim signal. Priority unit PR6 determines, if both processors have generated a claim signal, which is to be granted access and controls bi-stable CLSPSO, bi-stable CLSO also being set via OR gate 6. Bi-stable CLOKSAO is then set to generate a claim granted signal and reading of locations SBO1 and/or SBO2 may be effected followed by modification and writing back. Bi-stable CF(2) is then reset by the process 2 which results in bistable CLRQSAO and CLOKSAO being subsequently reset to indicate that the claim access is completed.