GB1444288A - Error correction - Google Patents

Abstract

1444288 Error detection and correction INTERNATIONAL BUSINESS MACHINES CORP 10 Dec 1974 [8 Jan 1974] 53271/74 Heading G4A In apparatus for the detection and correction of a single error occurring in a string of BCD data digits N 1 to N 10 scanned from a label and stored in a shift register 10, Fig. 4, the string including two check digits C 1 , C 2 formed from the original data digits N 1 <SP>(0)</SP> to N 10 <SP>(0)</SP> by the equations the "syndrome digits" are calculated. If both syndrome digits S 1 and S 2 are non-zero, the ith data digit is in error where and its corrected value is If only one of S 1 or S 2 is non-zero, the error is in one of the check digits C 1 , C 2 , whereas if S 1 and S 2 are both zero there is no error. In a generalization, there maybe more or less than 10 data digits N i and the number 11 is then replaced by a prime number greater than the number of data digits. The syndrome digits S 1 , S 2 are formed by a modulo 11 adder 16 via registers 12, 14, gates 19, 21 and a binary counter 20 (for repeated addition). The syndrome digits S 1 , S 2 are stored in a register 18, whence S 1 <SP>-1</SP> and S 2 are formed in decimal form by an inverse decoder 22 and a decoder 24 respectively, the circuit of inverse decoder 22 being given in Fig. 8 (not shown). Each decoder produces a decimal output on one of lines 1-10, the two outputs being fed to an array multiplier 26 to form S 1 <SP>-1</SP>S 2 (mod 11). The array multiplier 26, Fig. 6, comprises a square grid of wires 1-10 by 1-10, outputs being fed from all the crosspoints of the grid to ten OR gates 42a-42j. The inputs of, say, OR gate 42a, which leads to a 1 output of the array multiplier, originate from all those crosspoints (x, y), i.e. (1, 1), (2, 6), (3, 4), ... (10, 10), where xy#1 (mod 11). The decimal output i of the array multiplier 26 is stored in a register 28, whence it is used at the appropriate time as a disabling signal to block the data digit N i when the data string is being read-out of register 10 via an AND gate 34. The value - S 1 formed by a complementer 30 is then added to N i and the result conveyed to the output via an AND gate 36. The circuit of the complementer 30 is given in Fig. 9 (not shown). The Specification also discloses a method of correcting two data digits when their positions in a data string are known. The label may be marked with a bar code and may be optically scanned.