GB1423319A - Fast acting direct current clamping circuits - Google Patents

Abstract

1423319 Clamping circuits AMPEX CORP 9 May 1974 [14 June 1973] 20423/74 Heading H4F A clamping circuit operating to clamp the video signal at point 62, Fig. 3, to a clamp reference voltage supplied to a comparator 64 includes a holding capacitor 68 connected to point 62, the holding capacitor, during each line synchronizing interval, being first charged negatively by a negative current source 67 in response to a signal from control logic 65 to a voltage lower than that corresponding to the clamp reference voltage, and subsequently being charged positively by a positive current source 66 in response to a further signal from control logic 65, the positive charging being stopped when comparator 64 detects that the voltage at point 62 corresponds to the clamp reference voltage. Each horizontal synchronizing pulse separated by sync stripper 50 produces pulses on lines 101, 102, Fig. 5, forming part of the control logic 65, which pulses set monostable multivibrator 106 to enable AND gate 104 and hence activate negative current source 67; the output of the multivibrator 106 further sets flip-flop 111 and disables AND gate 103. When monostable multivibrator 106 resets, after less than half the horizontal sync pulse interval, AND gate 104 is disabled, negative current source 67 is deactivated, and AND gate 103 is enabled, due to flip-flop 111 being set, to activate positive current source 66. When comparator 64 detects that the voltage at point 62 corresponds to the clamp reference voltage AND gate circuit 83<SP>1</SP> provides a pulse to reset flip-flop 111 and so disable AND gate 103 and deactivate positive current source 66, holding capacitor 68 maintaining its voltage during the following line scan period.