DE2418546A1 - FAST DC TERMINAL CIRCUIT - Google Patents

Description

Patent Attorneys Dipl.-In'J. RWeickmann,

Dipl.-Ing. H.WeickmanN; Di'-l.-Phys. Dr K. Fincke Dipl.-Ing. F. A. Weickmann, Dipl.-Chem. B. Huber

8 MUNICH 86, DEN

PO Box 860 820

MÖHLSTRASSE 22, CALL NUMBER 98 39 21/22

AMPEX C0RP0MTI0N

401 Broadway, Redwood City, California 94063 / USA

Fast DC clamping circuit

The invention relates generally to a clamp circuit and, more particularly, to a high speed DC clamp circuit which can hold a signal at a desired voltage level.

In some electrical signal processing devices, the signal processing causes errors in the voltage level related to the signal. It is therefore important to restore the signal to the correct reference voltage level sometimes this makes it desirable or necessary eliminates the errors caused during signal processing. If this preparation is carried out quickly fast acting clamping circuits must be used. Conventional fast clamping circuits have been used heretofore felt to be disadvantageous because they have used capacitive reactive components switched directly into the video signal path.

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The dummy components led to tilting phenomena in the video signal. In addition, this results in a lift-to-close path Fast switching to the video signal path leads to undesired needle-pulse effects in the video signal, the Interrupt information.

The invention has the object of avoiding these disadvantages and one in particular for time base error correction arrangements of the type described below to provide a suitable clamping circuit with the DC deviation error in one Signal can be eliminated. The aim of the invention is to provide a fast acting and reliable DC clamp circuit indicate by which the DC offset error of a video signal is corrected on a line-by-line basis can. The expression line-to-line here refers to consecutive ones Video lines.

This object is achieved by the features specified in claim 1.

Here, the input and output of a DC clamp circuit connected to a node in the path of the signal to be maintained at a desired reference voltage. The input and output of the clamping circuit are connected to one another via isolating circuits, so that the Operation of the clamping circuit does not lead to undesirable effects in the signal path. The clamping circuit is a comparator which is controlled to compare part of the signal with a reference signal. One on the comparison A responsive current source accordingly supplies current to a storage device, so that a desired voltage level is always available in the storage device.

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The output of the memory device is via one of the isolation circuits connected to the node of the signal path so that the voltage at the node assumes a value which is determined by the instantaneous value of the voltage stored in the memory device. When the reference voltage of the signal deviates from the desired level, the voltage at the node is correspondingly determined by the current source brought back to the correct level as the current supplied to the storage device is the same as that stored in it Holds voltage at a level that corresponds to the correct level of the signal reference voltage.

The fast clamping circuit according to the invention thus has the advantage of being isolated from the signal path. As will be explained in more detail below, the video signal occurs neither by any reactive components nor by any switch elements that are directly connected to the signal path stay in contact. Another typical property of this clamp circuit is its extremely fast response; the clamping circuit works so fast that eie 3e video line of a video signal during the sync pulse peak of the horizontal blanking interval can jam "

In the following, exemplary embodiments of the invention are to be explained in more detail, namely:

Fig. 1 is a block diagram of a time base error correction arrangement ;

Figure 2 is a detailed block diagram of the time base error correction arrangement ;

3 shows a block diagram of an inventive constructed and in the time base error correction arrangement according to

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Fig. 2 clamping circuit used;

FIG. 4 shows a detailed circuit diagram of the clamping circuit according to FIG. 3; and

Fig. 5 is a detailed circuit diagram of another embodiment £ orm one in the clamping circuit according to 4 usable control logic circuit.

Figure 1 generally shows the use of the present invention in which a time base error correction arrangement is employed Records video signal from a video tape recorder and any timing error in that video signal relative to a time reference waveform determined. The video signal is delayed and corrected according to a measured time base error Video signal delivered at the output. Fig. 2 shows a time base error correction arrangement in which a plurality Fixed delay lines and equalizer 11 connected to an input line 12 to form a series signal path recording the video signal from the video tape recorder. Venn the video signal through this one behind the other Delay lines and equalizer 11 occurs, it is sent to the different connection points of the delay lines and equalizer 11 delayed differently, one of these Connection points is selected by a detector circuit and connected to an output. The detector circuit comprises a number of sync pulse detectors 13 and sequence detectors 14, and an enable selection pulse generator 16 and determines that connection point two delay lines and equalizer 11 on which a leading edge of a video sync waveform, in this case for a horizontal line, for the first time after a corresponding leading edge of a time horizontal reference signal

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Occurs during the course. If this is determined, one of the video switches 17 and switch control circuits 18 connects Switching circuit the selected connection point with an output line 19, through which the video signal is a video output 21 can be supplied.

To explain this mode of operation, it should be assumed that the video synchronizing waveform is just the first delay line 11 leaves and that at this point the enable selection pulse generator 16 has a leading edge of the time horizontal reference waveform is fed. The enable selection pulse generator in turn gives as below will be explained in more detail, a signal to one of the inputs of each of the order detectors 14 from. The remaining one Input to each of the order detectors 14 is thereby prepared and can respond to the respectively assigned sync pulse detector 13 via an AND gate 23. Shortly thereafter the leading edge of the video sync waveform reaches a junction 22 between the first and second 'Delay line 11 and causes the associated sync pulse detector 13 for outputting a switching signal to the assigned sequence detector 14, which in turn controls the Söhalter control circuit 18 and the associated video switch 17 operated. That from connection point 22 to output line 19 The transferred video signal passes through a series of output correction and processing stages and arrives at the video output 21.

However, the detector circuit not only determines the coincidence of the time-horizontal reference signal waveform and of the video sync waveform. It is unlikely that the leading edge of the time horizontal reference waveform and the leading edge of the video sync waveform each time, exactly at the same time, at one of the connection points of the delay lines 11 occurs. The detector circuit therefore determines the first leading edge of the video sync waveform that leads to

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the corresponding leading edge of the time horizontal reference waveform follows. The detector circuit also does not respond to the mere coincidence of both video sync peaks and reference sync peaks (which are so named because of their finite width), as this would not satisfy the "later" condition, according to which the first leading edge of the video sync waveform is "later" than the leading edge of the time horizontal reference waveform is to occur. In order to enable this "earlier" and ¹¹ later "function, each of the sequence detectors 14 has a gate 20 which is coupled in terms of alternating current to a resettable and resettable (RS) flip-flop 24.

In operation, the enable selection pulse generator 16 outputs via line 26 corresponding to the leading edge of the time horizontal reference waveform an actuation signal to the gate 20 from. The actuation signal is sent to the gate via a J input of the sequence detector 14, so that this is fed to the via the AND gate 23 with the connection point 22 connected sync pulse detector 13 can respond. When the leading edge of the video sync waveform occurs at connection point 22, the AND gate 23 responds to this by connecting it to a J 'input of the Sequence detector 14 emits an output signal. However, previously this gate 20 was used by the enable selection pulse generator 16 prepared; the J 'input can thus respond to the output signal of the AND gate 23 and thus tilt the flip-flop 24 into its set position. The output of the gate 20 is connected to a set input S.

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of the flip-flop 24 AC-wise coupled, while a K input of the sequence detector 14 AC-wise with a Reset input R is coupled in such a way that the set input S and the reset input R are set to certain polarities address the signal transitions. Because of these conditions, the flip-flop 24 is only then in its set position tilted when first on line 26, release selection pulse is transmitted and then the output of the AND gate 23 is recorded.

When the flip-flop 24 is in the set position, its Q output signal is high and actuates the associated one via a data input D. Switch control circuit 18, which thus takes over the setting position and via a « Q output signal closes the video switch 17. The flip-flops 24 are activated by the trailing edge of the enable selection pulse tilted back on line 26 to its reset position. The K input of each of the order detectors is with AC-coupled to the flip-flop 24 and only responds to a specific polarity of logical transitions, i. e. in the case considered here, on the polarity of those transitions that occur on the trailing edge of the enable selection pulse the line 26 are assigned. Due to the puncture limitation of the order detectors 14 by the above logical transitions, only that connection point of the delay lines 11 is selected at which the first leading edge of the video sync waveform follows an occurring leading edge of the time horizontal reference waveform.

If a connection point has been selected, the Q output signal switches one of the flip-flops 24 in addition to actuating the switch control circuit 18 via an OR gate 29 a lockout selection pulse generator 28. Each of the entrances

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of the OR gate 29 is, as shown, each connected to one of the flip-flops 24 emitting the Q output signal. The blocking selection pulse generator 28 inputs each of the AND gates 23 via a line 31 to one input each Signal and thus prevents the AND gates 23 from responding to subsequent signals from the sync pulse detectors 13. A selection made once thus prevents further actuation of the remaining switch control circuits 18.

The line 3Ί still connects the. Lockout selection pulse generator 28 with the clock inputs C of each of the switch control circuits 18 in order to convert them into a logical through the current To set level at data input D certain position. In the present example, the data input D is the Q output signal of the associated flip-flop 24 supplied. Accordingly, a switch control circuit 18, which in the course of the foregoing Measurement of a video line interval was tilted into its set position when a lockout selection pulse occurs on the Line 31 flipped into its reset position, since the data input D, provided that it is not the same Connection point has been selected, shows a logical zero. In the opposite case occurs at the data input D of the selected Switch control circuit 18 has a signal with a logic 1, which is directly a signal of the clock input C Lockout selection pulse generator 28 follows. The switch control circuit 18 thus assumes its betting position. In addition, the assigned video switch 17 is actuated accordingly.

The mode of operation of the time base error correction arrangement described so far falsifies the leading edge of the video synchronization signal curve appearing on output line 19 by introducing a time shift error. In particular

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can match the leading edge of the video sync waveform with the leading edge of the video signal as seen on an in The connection point located in the direction of advance occurs coincide when the detector circuit selects a connection point to which a greater delay time is assigned than the previously selected connection point. In other words, the video sync waveform becomes invalid extended. It is therefore an extension protection circuit 32 is provided that this erroneous leading edge of the output Video sync waveform.

In detail, this is achieved in that the video signal on the output line 19 through a video gate 33 of the Extension protection circuit 32 occurs, and that the video gate according to the sequence of signals on the input line 12 to the delay lines 11 and the output line 31 is actuated by the lock selection pulse generator 28. A gate control circuit 34 has a for this purpose on the leading edge of the video sync waveform on the Input line 12 responsive set input to the Gate control circuit 34 toggles into its set position and thus the video signal "fades out" via the video gate 33. The gate control circuit 34 remains in its set position until you A signal is supplied via line 31 which indicates that a connection point of delay line 11 has been selected became. This signal occurs substantially simultaneously with the leading edge at the selected connection point. Of the Gate control circuit 34 is thus a reset signal via an OR gate connected to a reset input supplied, which flips it into its reset position and "fades in" the video signal again. This mode of operation of the gate control circuit 34 and the video gate 33 suppresses effectively

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those areas of the video sync waveform that when switching from one connection point of the delay lines 11 to another, in the direction of progress afterwards lying connection point are wrongly caused. To the undesirable but possible consequence that the gate control circuit 34 does not receive a reset signal from the Lockout selection pulse generator 28 receives, to avoid, the reset input of the gate control circuit 34 via an OR gate alternatively the video sync waveform over a line 36 from the connection point at the output of the last in Delay line connected in series. This "additional return" signal serves as a lock release pulse, the sets the video gate 33 in its "on" state, which enables the passage of the video signal to the video output 21.

Furthermore, circuits are provided with which one of the Connection points of the delay lines can be arbitrarily connected to the output line 19 if the Video waveform is outside of the delay range provided by the detector circuit and the switch circuits for connection. The complete loss of the video signal on Video output 21 is thus avoided j it is preferred that a signal appears at the video output 21, even if it has timing errors. For this purpose there is an AND gate circuit 37 provided with an AND gate 38, whose Inputs to one of the δ output signals of the individual Switch control circuits 18 respond. In the event that all switch control circuits 18 are in their "off" states are located, the AND gate 38 provides an output signal. If this happens, the output signal of the AND gate becomes ^ 38

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inverted and via an OR gate 39 with the output one of the switch control circuits 18 connected line 27, via which it connects the associated video switch 17 operated independently of the actual state of the switch control circuit 18. In the present case, the AND gate is circuit 37 is connected to the video switch 17 assigned to a central connection point 41. The middle one Connection point 41 is in the middle between the input and the output of the delay lines connected in series 11.

At the input of the interconnected delay lines is a slow clamp circuit 46, i.e. a Clamping circuit with slow timing is connected and the video output is a fast clamping circuit 47, i.e. a fast-responding clamp circuit connected. The individual use of slow and fast clamping circuits in connection with video signal systems is of course known. However, Eb was found to be the advantageous mode of operation of the time base error correction arrangement, in which the video signal is transmitted through various delay lines and occurs through various switching circuits, not least due to the fact that the fast clamping circuit 47 is arranged at the video output 21 for direct current processing. The slow clamp circuit 46 is conventional developed and compensates for any error due to DC deviations of the video signal slowly, d * .h. over a multitude Horizontal line periods. The slow clamping circuit 46 mentioned here thus has a time constant that is greater is considered a single horizontal line period and which usually takes 5 to 20 horizontal line periods before it stabilizes at a mean DC correction value «This can lead to errors due to mean DC deviations are eliminated so "that any when the video signal passes through the delay lines 11 and the

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Video switch 17 caused DC errors in the correction range of the fast clamping circuit 47 is. After the DC reprocessing by the slow Kl switch 46, the video signal occurs a sync signal processing network with a synchro-height limiter 51, which has a negative deflection of the synchronous waveform is limited, with a separating circuit separating the synchronous waveform from the video signal 52, with an amplifying rising edge generator 52 connected in series with the separating circuit 52, the new leading edge of the synchronous waveform generated, and with a summing circuit 54, the regenerated synchronous waveform to the video signal from the synchronous height limiter 51, which is limited in its synchronous signal height.

After the synchronization signal processing, the video signal is transmitted through one of the defined delay lines 11 existing first Zeitb ^ Ls correction stage. To after this correction and after passing through the extension protection circuit 32, the video signal becomes a second, off with each other connected delay lines 56 supplied to existing time base correction stage. The second time base correction stage corresponds essentially to the delay lines 11 and the switching circuits described above.

In the embodiment shown, the interconnected delay lines 11 of the first time base correction stage enable a fairly coarse correction of the time base error, since the values of the fixed delay lines 11 are greater than those of the delay lines in the second time base correction stage. By using a first set of delay lines with relatively large values on which a second S _a tz delay lines follows with relatively small values to economic cost per delay line can be achieved in the correction area.

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The second time base correction stage is followed by the above-mentioned fast clamping circuit 47, which within each Horizontal line period ensures compliance with a desired direct current level. The phrase "fast clamp circuit 47 "refers to the ability within each video period, i.e. in this case one horizontal line period, to adjust to the desired DC level. The fast clamp circuit 47 responds during the video sync spike of each horizontal line. The advantageous mode of operation the time base correction arrangement is in particular through the combination of the slow clamping circuit 46 am Input for the switched video signal and the subsequent fast clamping circuit 47 at the output is determined.

The invention resides in the particular construction and operation of the fast clamp circuit 47 _f which are specifically suitable for the approximation of the DC voltage to a desired DC voltage level within each of the horizontal line period of the Videiosignals. The clamping circuit according to the invention is also suitable for adjusting other signals, in particular periodic or repetitive signals, to a desired DC voltage level. The fast clamp circuit of the present invention shown in detail in Figures 3-5 has the characteristic advantage that it is isolated from the video signal path. In the embodiment of the fast clamping circuit according to FIGS. 3 and 4, a video signal path 61 extends from an output of the second stage of interconnected delay lines 56 shown in FIG tied together. As will be shown in more detail below, the video signal path 61 does not lead - via any-

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what reactive component !! still over any switch, which are directly connected to the clamp connection point 62. Another characteristic of this special clamping circuit 63 is their extremely fast response. It responds quickly enough to cover every line of video during the sync pulse peak of the horizontal blanking interval to clamp.

The operation of the clamping circuits according to FIGS. 3 and 4 will be explained below. A comparator 64 speaks with its one input to a video line voltage at clamp connection point 62 and with its other input a clamp reference voltage. Depending on whether the video line voltage at the terminal connection point 62 during measurement operation is above or below the clamp reference voltage, an output of comparator 64 takes one of two discrete ones Values and thus corresponds to either a logical one or a logical zero. One from a sync input signal effectively switchable control logic circuit 65 speaks to the Output signal of the comparator 64 and switches either a positive constant current source 66 or a negative Constant current source 67 depending on the logic state of the output signal of the comparator 64. The sync input signal is separated from the video synchronization signal with the help of a synchronizing separation stage 50 » With the aid of a buffer amplifier 69 designed as an operational amplifier, a holding capacitor 68 determines a supply or decreasing voltage proportional to the charge on hold capacitor 68 at clamp junction 62 and added or thereby subtracts an appropriate DC offset to or from the video signal level. A resistor 71 insulates here the low-resistance output of the buffer amplifier 69 from the terminal connection point 62. The inputs of the comparator are high resistance and thus the clamp connection point 62 is of both ends of the clamp circuit 63 and its internal switching operation isolated.

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If the video sync signal peak at the terminal connection point 62 is in operation, e.g. below the terminal reference voltage, so The comparator 64 switches on the positive constant current source 66 via the control logic circuit 65, via which a steady current Current in the holding capacitor 68 flows j the voltage at Clamping connection point 62 thus increases rapidly. As soon as the voltage at the clamp connection point 62 reaches the clamp reference voltage exceeds, the output signal of the comparator changes

64 the logic state, the control logic circuit 65 switches the positive constant current source 66 and the clamp connection point 62 remains at the correct DC voltage. Apart from that with the exception of the following, the clamping circuit operates when the video sync signal peaks are above the clamping reference voltage at the clamp connection point 62 accordingly. The control logic circuit 65 only then switches both constant current sources 66 and 67 when the voltage at clamp connection point 62 exceeds the clamp reference voltage in a particular direction exceeds. The reason and the mode of operation of this unidirectional response of the control logic circuit

65 is to be explained in more detail below in connection with the circuit diagram according to FIG. The entire search string for the correct DC voltage takes place within the temporal width of the horizontal sync signal peak. Is the right one When the deviation is reached, it is stored in the holding capacitor 68 for the duration of the subsequent video line.

It should be emphasized that the construction and operation of the fast clamping circuit 47 according to FIG. 3 is based on digital logic operating at discrete levels, in which the correction of the deviation error except for the variable charge in the holding capacitor 68 is carried out with the aid of discrete current and voltage levels will. This operating principle is also the reason for the extraordinary reliability and the fast operation of the clamping circuit. aside from that

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the use of a logic controller instead of an analog controller reduces the manufacturing cost of the network considerable.

In the embodiment according to FIG. 4, the comparator 64 consists from a TTL (transistor-transistor-logic) logic module with an output 76 connected to the control logic circuit 65 is coupled via an input converter stage 77. In this case, the input converter stage 77 has a MECL converter (Motorola-Emitter-coupled logic) on which the TTL logic at output 76 in the MECL logic on which the control logic circuit 65 is based, converts. The input converter stage 77 emits separate signals at its output via lines 78 and 79 complementary state to two AND gates 81 and 82, which operate the positive and negative constant current sources 66 and 67, respectively. Another UM) gate 83 is with his one input directly to line 78 and with its second input via an RC delay network composed of a resistor and a capacitor connected to line 79. It is used to block AND gates 81 and 82 via an RS flip-flop 84, the constant current sources corresponding to a special transition of logic states at the output of the comparator 64 turns off. In particular, the control logic circuit 65 according to FIG. 4 switches the constant current sources 66 and 67, As mentioned briefly above, only when the DC voltage at the terminal connection point 62 has the desired terminal reference voltage from bottom to top (from 0 to 1). This mode of operation has the important advantage that the corrected voltage at the terminal connection point 62 is ultimately always slightly above the terminal reference voltage and not depending on the polarity of the added correction DC voltage comes to lie above or below. In this way, there is greater line-to-line accuracy the clamping level ensured.

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Assuming the sync peak at the clamp connection point 62 is above the terminal reference voltage when the control logic circuit 65 receives the sync input is supplied and is there adapted to the MECL logic by a converter 86, sets an output signal of the AND gate 87 the RS flip-flop 84. The RS flip-flop 84 prepares now in turn the two AND gates via an S output signal and 82 for switching on. Depending on the logic state of the comparator 64, one of the AND gates 81 and 82 is then over the lines 78 and 79 switched through and. as a result, the respectively suitable of the two constant current sources 66 and 67 switched on. Assuming that the video signal is originally above the clamp reference voltage, switches the comparator 64 and the control logic circuit 65 apply the negative constant current source 67 to decrease the voltage at clamp connection point 62. The video voltage at clamp connection point 62 thus exceeds the clamp reference voltage from top to bottom during the sync signal peak, whereupon the comparator 64 changes its state and thus the logic conditions of the complementary lines 78 and 79 on its Output switches. After this switchover, the AND gate 82 switches off the negative constant current source 67 and the AND gate 81 switches the positive constant current jellyfish 66 on. The voltage on the holding capacitor 68 speaks to this by increasing the voltage level at clamp connection point 62 until the clamp reference voltage, albeit in this case directed from bottom to top, is again exceeded. The logic state on lines 78 and 79 becomes again switched and the RC delay network 89 at one of the inputs of the AND gate 83 holds the previous voltage state upright at this entrance. The AND gate 83 therefore responds to the changed voltage state on its other Input by emitting an output signal which resets the RS flip-flop 84. The RS flip-flop 84 is thus in

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its original position tilted back, in which the AND gates 81 and 82 from the Q output signal of the RS-FlJp-flop 84 ineffective be switched. The above sequential modes of operation run entirely within the sync peak a horizontal blanking gap. The one shown, connected between the converter 86 and the AND gate 87 RC network allows selective response so that only the leading edge of the video sync waveform has the RS flip-flop '84 sets.

For applications in which higher resolutions are desired v / ground, the embodiment of the control logic circuit 65 according to FIG. 4 is carried out in the fast clamping circuit 63 a control logic circuit 65 'of FIG. 5 is replaced. the Control logic circuit 65 'operates in the same way as the Control logic circuit 65 shown in FIG. 4 is activated. In contrast to the embodiment according to FIG. 4 switches the activated control logic circuit 65 ' both positive and negative power sources 66 and 67, respectively, to during the horizontal sync pulse interval regardless of the actual voltage level of the sync pulse peak occurring at the terminal connection point 62 To provide power to the holding capacitor 68. This is done in detail by the synchronizing separation stage The synchronizing input signal separated from the video sync pulse is fed to a MECL logic converter 86 'which accordingly emits separate complementary pulse signals on lines 101 and 102. The impulses of the The pulse signals emitted on the line 101 serve as enable pulses for AND gates 103 and .104, the Enable pulses ensure that the current sources 66 and 67 are only switched on during the sync peak interval are. The pulse signals emitted by the converter 86 are also supplied to an AND gate circuit 87 ',

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which serves as a pulse shaper and a brief pulse to trigger a monostable multivibrator 106 generated. The multivibrator 106 responds to the short-term impulse in that it is in its quasi-stable State switches and generates a pulse, which shortly after the occurrence of the leading edge of the horizontal sync pulse begins at the clamp connection point 62 and with the return of the multivibrator 106 in the stable Switching state ends. The end of the pulse is determined by an RC network 107 of the multivibrator 106. In the illustrated embodiment, the components are of the RC network 107 is preferably selected so that the quasi-stable switching state then ends and the delivered Pulses thus have an interval of less than 1/2 the interval of the horizontal sync pulse.

The Ö output of the multivibrator 106 is connected to a second Input of AND gate 104 connected. In the quasi-stable switching state, the output signal fulfills the Q output together with the enable pulse of the converter 86 * the conditions of the AND gate 104 and switches the negative Voltage source 67 on. At the same time there is the Q output of multivibrator 106 in the complementary switching state and thus switches AND gate 103 ineffective. The ineffective AND gate 103 ensures that the positive current source 66 in the switch-on interval of negative power source 67 remains switched off.

When the negative current source 67 is switched on, the storage or holding capacitor 68 is charged negatively, until the positive power source 66 delivers positive power.

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At the end of the quasi-stable switching state of the multivibrator 106 inverts the G output of multivibrator 106 back to that switching state by sending it to a second input of the · AND gate 103 as a further enable signal serves. At the same time, the switching state of the δ output signal of the multivibrator 106 returns to that Switching state back, which switches the AND gate 104 and thus the negative current source 67 ineffective. The Q output signal of the multivibrator 106 is also fed to a set input S of a flip-flop 111. If the Multivibrator 106 returns to its stable switching state, the flip-flop 111 is accordingly on its Q output a third and final enable signal to a third input of the AND gate 103.

The three enable signals at the inputs of the AND gate provide the condition for switching on the positive current source 66, which then feeds positive current to the storage capacitor 68. If the storage capacitor 68 is supplied with positive current, its voltage level rises to the desired direct voltage at the terminal connection point 62. When the level of the voltage applied to the storage capacitor 68 has risen to a level at which the voltage at the terminal connection point 62 has reached a level corresponding to the terminal reference voltage at the input of the comparator 64, the comparator 64 causes a transition in ^{the input of the control logic circuit 65 f} logical state. MECL logic converter 77 'is responsive to the logic state transition by causing a change in logic states on complementary lines 78 * and 79' in a selected transition direction. ^{An AND gate 83 f is} coupled to the lines 78 * and 79 *, which on!.: The change in the logical states of the lines 78 'and 79' in the desired transition direction generates a short-lasting pulse.

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continuous pulse is sent to the reset input R of the flip-flop supplied, whereby the flip-flop 111 is set in the state that the enable signal from the input of the AND gate 103 turns off. By switching off the enable signal, the AND gate 103 and thus the positive Current source 66 switched ineffective. The power supply from the storage capacitor 68 is thus terminated and the stored Voltage is at least for the remaining interval of the horizontal line of the video signal on one The level corresponding to the desired level at the clamp connection point 62 is maintained.

When the flip-flop 111 is reset, the original conditions of the monostable multivibrator 106 become and the flip-flop 111 restored, whereby the AND gates 103 and 104 and thus the positive and the negative Current source 66 or 67 are switched ineffective. They remain until the next sync pulse occurs at the terminal connection point 62 in their original switching states. When the next sync pulse occurs causes the sync signal separation stage 50 via the raonostable Multivibrator 107 repeats a cycle of operation by first supplying negative and then positive current will.

As has been shown, the embodiment of the control logic circuit 65 'of FIG. 5 enables the storage capacitor 68 first negative current is supplied, which the stored voltage is considerably below that at the terminal connection point 62 lowers the desired level and that then the storage capacitor 68 as long as positive current is supplied until the stored voltage reaches the level desired at clamp junction 62. This mode of operation in the event of original deviations in the voltage of the

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Sync pulse at the terminal connection point 62 both according to below as well as above of the desired level. By initially reducing the stored voltage and subsequent increase, the tension at the clamp connection point can 62 to be resolved to a very high degree. Resolutions of fractions of a percent of the synchronous pulse voltage levels can easily be reached.

On the direct current processing through the separate clamping circuit 47 follows, as shown in FIG. 2, a pin correction stage 91 as the last time base error correction stage. The fine correction stage 91 preferably consists of one or more voltage-variable delay lines, responsive to a horizontal reference voltage and, in color systems, to a color subcarrier reference voltage. One such a time base error correction stage is described in U.S. Patent 3,213,192. A circuit 92 then processes the last stage is the video signal, i.e. it regenerates or adds new sync signals. Circuit 92 is conventional educated.

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Claims (1)

Claims Clamping circuit for holding a circuit point at a predeterminable reference voltage, characterized by a comparator (64) - which has one input coupled to node (62) and that to another The reference voltage can be supplied to the input by a storage device (68) which is used for direct voltage correction required fourth by which node (62) is to be kept at the reference voltage, by one connecting the memory device (68) to the node (62) and the node (62) a value determined by the instantaneous value of the direct voltage correction stored in the storage device (68) the voltage holding buffer stage (69), by one with the Current source (66, 67) connected to the storage device (68), which supplies current to the storage device (68) and thus the changes stored value required for the DC voltage correction, and by a the output of the comparator (64) with the current source (66, 67) connecting control logic circuit (65, 65 ') based on the logic state at the output of the comparator (64) responds and controls the current source (66, 67) accordingly so that the value of the DC voltage correction in the memory device (68) increases or decreases. 2 «clamping circuit according to claim 1, characterized in that g e k e η η, that the storage device (68) is designed as a capacitive voltage store. 3 » Clamping circuit according to one of claims 1 or 2, characterized in that the control logic circuit (65 *) responds to the signal state at the switching point (62) and emits control signals to the current source (66, 67) which the 409881/0762 _ 24 - Memory means (68) to one of the reference voltage bring corresponding value "and that the control logic circuit (65 ^) the control signals and thus the current source (66, 67) turns off when the comparator (64) detects that the voltage level at the node (62) has reached the reference voltage. 4. Clamping circuit according to one of the preceding claims, characterized in that the comparator (64) and the control circuit (65 ') via an impedance separator are connected to the node (62). 5. Clamping circuit according to claim 4, characterized in that the impedance separation stage by a high impedance of the comparator (64) is formed. 6. Clamping circuit according to one of the preceding claims, characterized in that the current source has a first (67) and a second (66) current source that the first current source (67) emits current in response to first control signals of the control logic circuit (65 *) the storage device (68) charges in a first direction to a voltage which differs from the voltage corresponding to the reference voltage and that the second current source (66) then delivers current to the storage device (68) in ^{response to second control signals from the control logic circuit (65 1)} and thereby charging it in a second direction opposite to the first until the stored voltage reaches the voltage corresponding to the reference voltage. 7. Clamping circuit according to claim 6, characterized in that the first current source (67) has a negative power source and the second power source (66) is a positive power source and that the negative power source 409881/0762 the storage device (68) charges until "until the stored voltage reaches a level that is lower than the voltage corresponding to the reference voltage. 8. Clamping circuit according to one of claims 6 or 7, characterized in that the control logic ^{circuit (65 1} ) switches off the power supply from the second power source (66) to the storage device (68) when the comparator (64) at the switching point (62) a determines the voltage corresponding to the reference voltage. 9. Clamping circuit according to one of the preceding claims, characterized in that the switching point (62) lies in a signal path leading to periodic pulse signals and that the control logic circuit (65 *) responds to each on Switching point (62) occurring pulse signal emits the control signals. 10. Clamping circuit according to claim 9, characterized in that the periodic pulse signal is a video signal with horizontal sync pulses which are to be kept at a nominal voltage level corresponding to the reference voltage and that the control logic circuit (65 ¹ ) has a synchronizing separation stage (50) which Separates horizontal sync pulses from the video signal. 11. Clamping circuit according to one of claims 9 or 10, characterized in that the control logic circuit (65 ¹ ) has a monostable multivibrator (1O6) on v / eist, which can be switched into its quasi-stable state by the pulse signal during a specified interval and that emits first control signal, and which returns to its stable state at the end of the specified interval, switches off the first control signal and emits the second control signal and that the 409881/0762 Control logic circuit (65 ¹ ) a first electronic gate (104) that is responsive to the first control signal and that enables the negative current source (67) for outputting current to the storage device (68) as well as a second electronic gate (104) that is responsive to the second control signal and the positive current source (66 ) has an electronic gate (103) releasing current to output current to the storage device (68), the second electronic gate (103) also responding to the comparator (64) for switching off the positive current source (66). 409881/0762