GB1410082A - Central processing unit - Google Patents
Central processing unitInfo
- Publication number
- GB1410082A GB1410082A GB826075A GB826075A GB1410082A GB 1410082 A GB1410082 A GB 1410082A GB 826075 A GB826075 A GB 826075A GB 826075 A GB826075 A GB 826075A GB 1410082 A GB1410082 A GB 1410082A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bus
- gates
- phase
- transfer
- aug
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3872—Precharge of output to prevent leakage
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- Shift Register Type Memory (AREA)
- Logic Circuits (AREA)
- Complex Calculations (AREA)
Abstract
1410082 Data processing systems TEXAS INSTRUMENTS Inc 29 Aug 1972 [31 Aug 1971 (7)] 8260/75 Divided out of 1410081 Heading G4A A single integrated circuit chip carries a parallel arithmetic unit, random access memory unit, instruction register and control circuitry interconnected by a common parallel bus 81 which is precharged during a first clock phase and is selectively discharged in the interval between the first and a second clock phase in order to transfer information between the units on the chip. A pair of transfer gates 87 are connected in series between bus 81 and earth 89, the bus is precharged during #1 via gates 91 and 85 (the same phase is used to transfer data from bus 81 to terminals A via gates 83), and at the termination of phase #1 data on terminals A are transferred through gates 85 to selectively discharge the bus 81. The disclosure is identical with that of the parent Specification 1,410,081.
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17666771A | 1971-08-31 | 1971-08-31 | |
US17667071A | 1971-08-31 | 1971-08-31 | |
US17666671A | 1971-08-31 | 1971-08-31 | |
US17666871A | 1971-08-31 | 1971-08-31 | |
US17666571A | 1971-08-31 | 1971-08-31 | |
US05/176,664 US4037094A (en) | 1971-08-31 | 1971-08-31 | Multi-functional arithmetic and logical unit |
US05/176,669 US3962684A (en) | 1971-08-31 | 1971-08-31 | Computing system interface using common parallel bus and segmented addressing |
GB4008372A GB1410081A (en) | 1971-08-31 | 1972-08-29 | Central processing unit of a computing system |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1410082A true GB1410082A (en) | 1975-10-15 |
Family
ID=27571196
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB827675A Expired GB1410083A (en) | 1971-08-31 | 1972-08-29 | Arithmetic logic unit |
GB823875A Expired GB1410084A (en) | 1971-08-31 | 1972-08-29 | Arithmetic logic unit |
GB826075A Expired GB1410082A (en) | 1971-08-31 | 1972-08-29 | Central processing unit |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB827675A Expired GB1410083A (en) | 1971-08-31 | 1972-08-29 | Arithmetic logic unit |
GB823875A Expired GB1410084A (en) | 1971-08-31 | 1972-08-29 | Arithmetic logic unit |
Country Status (1)
Country | Link |
---|---|
GB (3) | GB1410083A (en) |
-
1972
- 1972-08-29 GB GB827675A patent/GB1410083A/en not_active Expired
- 1972-08-29 GB GB823875A patent/GB1410084A/en not_active Expired
- 1972-08-29 GB GB826075A patent/GB1410082A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB1410083A (en) | 1975-10-15 |
GB1410084A (en) | 1975-10-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PE20 | Patent expired after termination of 20 years |