GB1404015A - Emitter-coupled-logic-circuits - Google Patents

Emitter-coupled-logic-circuits

Info

Publication number
GB1404015A
GB1404015A GB3577372A GB3577372A GB1404015A GB 1404015 A GB1404015 A GB 1404015A GB 3577372 A GB3577372 A GB 3577372A GB 3577372 A GB3577372 A GB 3577372A GB 1404015 A GB1404015 A GB 1404015A
Authority
GB
United Kingdom
Prior art keywords
emitter
carry
signal
coupled
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3577372A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19712141415 external-priority patent/DE2141415C3/en
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB1404015A publication Critical patent/GB1404015A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • H03K19/0866—Stacked emitter coupled logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4806—Cascode or current mode logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Optimization (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

1404015 Carry generating circuit SIEMENS AG 1 Aug 1972 [18 Aug 1971] 35773/72 Heading G4A [Also in Division H3] A circuit for forming the "carry" signal in the addition of binary numbers comprises an emitter coupled pair to which input signals A and B are supplied (Fig. 4) and which are fed from a constant current source S, each input transistor feeding a further emitter-coupled pair controlled respectively by the opposite input signal and by the "carry" signal C in from the previous stage, and each emitter pair being emitter coupled to a third transistor having its base connected to a fixed potential (VR1 or VR2) and its collector connected to the load resistance R2 of an emitter follower output transistor. The output corresponding to the new "carry" signal is given by the equation
GB3577372A 1971-08-18 1972-08-01 Emitter-coupled-logic-circuits Expired GB1404015A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19712141415 DE2141415C3 (en) 1971-08-18 Series-coupled ECL circuit with several independently controllable current paths in a lower level

Publications (1)

Publication Number Publication Date
GB1404015A true GB1404015A (en) 1975-08-28

Family

ID=5817097

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3577372A Expired GB1404015A (en) 1971-08-18 1972-08-01 Emitter-coupled-logic-circuits

Country Status (3)

Country Link
FR (1) FR2150161A5 (en)
GB (1) GB1404015A (en)
IT (1) IT963948B (en)

Also Published As

Publication number Publication date
DE2141415B2 (en) 1975-06-26
DE2141415A1 (en) 1973-03-01
FR2150161A5 (en) 1973-03-30
IT963948B (en) 1974-01-21

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees