GB1387873A - Decoder for quadraphonic sound - Google Patents

Abstract

1387873 Quadraphonic decoders CBS Inc 11 Feb 1972 [24 Feb 1971] 6580/72 Heading H4 In a quadraphonic reproducing system for feeding loud-speakers at the four corners of a listening area with respective signals derived by a matrix, Fig. 1A, from two channel signals 10, 12, each comprising a respective predominant front signal R f or L f together with sub-dominant rear signals, R b and L b , of both sides in quadrature with different signals leading in each channel, and in which the matrix derives respective loud-speaker signals each having a predominant component L b , R b , L f or R f , together with subdominant signals of both sides, from the front if the predominant signal is from the rear, and vice versa, the signals are fed to the loud-speaker via amplifiers 100, 102, 104, 106, whose gains are controlled via a logic circuit, Fig. 1B, which is fed with signals derived from points in the matrix providing two pairs of signals, one pair containing sub-dominant rear components which are directly in phase, or in phase opposition, in the two signals while the other pair have subdominant front components in phase, or in phase opposition in the two signals. The signals in each pair are full wave rectified at 36, 38, 40, 42, and the two signals in each pair are compared in comparators 60 and 62. If only the rear signals L b and R b are present the inputs to comparator 60 will be equal and no output will result, while an output will be obtained, provided the L b abd R b signals are uncorrelated, from comparator 62. The comparator outputs are full wave rectified at 64, 66, fed through shaping networks and applied to control circuits 80, 82, which differentially adjust the gains of the amplifiers feeding the rear speakers relative those feeding the front speakers. Similarly if only the front signals L f and R f are present the gain of the amplifiers feeding the front loudspeakers is increased and that of the others reduced. An alternative form of matrix, the same as that of Specification 1,379,771 and a suitable logic circuit are described with respect to Fig. 4A and 4B (not shown). (For Figures see next page.)