GB1381489A - Method of manufacturing a semiconductor element - Google Patents

Method of manufacturing a semiconductor element

Info

Publication number
GB1381489A
GB1381489A GB6053271A GB6053271A GB1381489A GB 1381489 A GB1381489 A GB 1381489A GB 6053271 A GB6053271 A GB 6053271A GB 6053271 A GB6053271 A GB 6053271A GB 1381489 A GB1381489 A GB 1381489A
Authority
GB
United Kingdom
Prior art keywords
contact
dec
gold
semi
deposit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB6053271A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Licentia Patent Verwaltungs GmbH
Original Assignee
Licentia Patent Verwaltungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19702064281 external-priority patent/DE2064281C3/de
Application filed by Licentia Patent Verwaltungs GmbH filed Critical Licentia Patent Verwaltungs GmbH
Publication of GB1381489A publication Critical patent/GB1381489A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/902—Capping layer

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Die Bonding (AREA)
  • Thyristors (AREA)
GB6053271A 1970-12-29 1971-12-29 Method of manufacturing a semiconductor element Expired GB1381489A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702064281 DE2064281C3 (de) 1970-12-29 Halbleiterbauelement mit Metallkontakten aus Gold oder einer Goldlegierung und Verfahren zu seiner Herstellung

Publications (1)

Publication Number Publication Date
GB1381489A true GB1381489A (en) 1975-01-22

Family

ID=5792469

Family Applications (1)

Application Number Title Priority Date Filing Date
GB6053271A Expired GB1381489A (en) 1970-12-29 1971-12-29 Method of manufacturing a semiconductor element

Country Status (5)

Country Link
US (1) US3840398A (enExample)
JP (1) JPS5329990B1 (enExample)
BE (1) BE777392A (enExample)
FR (1) FR2120037B1 (enExample)
GB (1) GB1381489A (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2394894A1 (fr) * 1977-06-17 1979-01-12 Thomson Csf Dispositif de prise de contact sur un element semiconducteur
US4394678A (en) * 1979-09-19 1983-07-19 Motorola, Inc. Elevated edge-protected bonding pedestals for semiconductor devices
JPS5666253U (enExample) * 1979-10-26 1981-06-02
JPS5668466U (enExample) * 1979-10-30 1981-06-06
DE3039658A1 (de) * 1980-10-21 1982-05-06 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Mit edelmetall beschichtetes molybdaen und verfahren zu seiner herstellung
US4600658A (en) * 1983-11-07 1986-07-15 Motorola, Inc. Metallization means and method for high temperature applications
US4495222A (en) * 1983-11-07 1985-01-22 Motorola, Inc. Metallization means and method for high temperature applications
JPS6216269U (enExample) * 1985-07-15 1987-01-30
US6517944B1 (en) 2000-08-03 2003-02-11 Teracomm Research Inc. Multi-layer passivation barrier for a superconducting element

Also Published As

Publication number Publication date
FR2120037A1 (enExample) 1972-08-11
JPS5329990B1 (enExample) 1978-08-24
BE777392A (fr) 1972-04-17
US3840398A (en) 1974-10-08
FR2120037B1 (enExample) 1977-08-05
DE2064281B2 (de) 1976-09-30
DE2064281A1 (de) 1972-07-13

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee