GB1365218A - Memory cores - Google Patents

Abstract

1365218 Semi-conductor memory elements COMMISSARIAT A L'ENERGIE ATOMIQUE 10 May 1972 [12 May 1971] 21808/72 Heading H1K A memory element for a random-access dynamic memory comprises two electrodes 8, 10 capacitively coupled to a semi-conductor substrate 2, and a further electrode, e.g. constituted by a surface-barrier contact or a diffused or ionimplanted region 4 of opposite conductivity type to the substrate 2, aligned with the capacitive electrodes 8, 10. The electrode 8 furthest from the region 4 serves as a storage electrode, having applied thereto a fixed potential V 2 . Fig. 2a shows how charge injected from the region 4 is transferred to the depletion region beneath the storage electrode 8 by the application of appropriate potentials to the region 4 and the control electrode 10, which may be physically smaller than the storage electrode 8. Fig. 2b shows the element in its storage mode. Due to spontaneous minority-carrier generation and subsequent recombination of the stored charge the store is dynamic, requiring to be replenished at regular intervals. Read-out and erasure is illustrated in Fig. 2c, being effected by the application of the same potential V 3 to both electrode 10 and region 4, where |V 3 | > | V 2 | . For use in an array in which elements are accessed by simultaneous potentials applied along lines extending in two mutually orthogonal directions each element may be provided with two control electrodes such as 10, all three capacitive electrodes and the injecting region 4 being mutually aligned. In a memory device elements of the type described are arranged in an orthogonal array, all elements in a word line sharing a common strip-like injecting region 4. For a Si substrate the insulation of the capacitive electrodes 8, 10 may be silicon oxide or nitride, the electrodes themselves being Al or heavily doped Si.