GB1345464A - Electirc signal pulse conversion circuits - Google Patents

Abstract

1345464 Pulse synchronizing circuits, data transmission SIEMENS AG 31 May 1972 [4 June 1971] 25388/72 Headings H3T and H4P In an arrangement for converting asynchronous pulse signals at E into signals which are synchronized in duration and phase with clock signals at input T, the two signals control a bistable FF which has a first output A at which the synchronized signal are produced, and a second output which is connected to an input of an auxiliary circuit HS, the circuit HS having a second input fed with the asynchronous signal and an output C which is connected to a logic circuit 1, 2 whose output is connected to a preparation input J of bi-stable FF, such that it may be set only once during each input pulse at E. Initially output B of NAND 3 is "0", output C of NAND 4 is "1", reset input D of bi-stable FF is "1", output A is "0", and input E is "0". When E changes to "1", NAND 1 and inverter 2 supply a "1" on the J input of FF, so that, on the arrival of the leading edge of the next clock pulse at T, bi-stable FF switches to give a "1" on output A, and to change output B of NAND 3 to "1". NAND 4 thus now receives two "1" inputs, producing a "0" output which inhibits NAND 1 to cause input J of FF to revert to "0". On arrival of the trailing edge of the clock pulse, inverter 5 provides a "1" input to NAND 6 so that FF is reset to a "0" on output A. When the signal E reverts to its "0" state, the signal at B reverts to "0" and the signal at C reverts to "1".