GB1345464A - Electirc signal pulse conversion circuits - Google Patents
Electirc signal pulse conversion circuitsInfo
- Publication number
- GB1345464A GB1345464A GB2538872A GB2538872A GB1345464A GB 1345464 A GB1345464 A GB 1345464A GB 2538872 A GB2538872 A GB 2538872A GB 2538872 A GB2538872 A GB 2538872A GB 1345464 A GB1345464 A GB 1345464A
- Authority
- GB
- United Kingdom
- Prior art keywords
- output
- input
- nand
- signal
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
1345464 Pulse synchronizing circuits, data transmission SIEMENS AG 31 May 1972 [4 June 1971] 25388/72 Headings H3T and H4P In an arrangement for converting asynchronous pulse signals at E into signals which are synchronized in duration and phase with clock signals at input T, the two signals control a bistable FF which has a first output A at which the synchronized signal are produced, and a second output which is connected to an input of an auxiliary circuit HS, the circuit HS having a second input fed with the asynchronous signal and an output C which is connected to a logic circuit 1, 2 whose output is connected to a preparation input J of bi-stable FF, such that it may be set only once during each input pulse at E. Initially output B of NAND 3 is "0", output C of NAND 4 is "1", reset input D of bi-stable FF is "1", output A is "0", and input E is "0". When E changes to "1", NAND 1 and inverter 2 supply a "1" on the J input of FF, so that, on the arrival of the leading edge of the next clock pulse at T, bi-stable FF switches to give a "1" on output A, and to change output B of NAND 3 to "1". NAND 4 thus now receives two "1" inputs, producing a "0" output which inhibits NAND 1 to cause input J of FF to revert to "0". On arrival of the trailing edge of the clock pulse, inverter 5 provides a "1" input to NAND 6 so that FF is reset to a "0" on output A. When the signal E reverts to its "0" state, the signal at B reverts to "0" and the signal at C reverts to "1".
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19712127944 DE2127944A1 (en) | 1971-06-04 | 1971-06-04 | Integrable circuit arrangement for converting asynchronous input signals into signals synchronized with a system's own clock |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1345464A true GB1345464A (en) | 1974-01-30 |
Family
ID=5809913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2538872A Expired GB1345464A (en) | 1971-06-04 | 1972-05-31 | Electirc signal pulse conversion circuits |
Country Status (7)
Country | Link |
---|---|
BE (1) | BE784339A (en) |
DE (1) | DE2127944A1 (en) |
FR (1) | FR2141744B1 (en) |
GB (1) | GB1345464A (en) |
IT (1) | IT956030B (en) |
LU (1) | LU65452A1 (en) |
NL (1) | NL7207439A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2402880C2 (en) * | 1974-01-18 | 1982-01-21 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Fail-safe electronic circuit for converting electrical signals of different duration into signals of a certain duration |
US5087835A (en) * | 1991-03-07 | 1992-02-11 | Advanced Micro Devices, Inc. | Positive edge triggered synchronized pulse generator |
DE19844936C2 (en) * | 1998-09-30 | 2001-02-01 | Siemens Ag | Circuit for generating an output signal depending on two input signals |
DE102004031669B3 (en) * | 2004-06-30 | 2006-02-09 | Infineon Technologies Ag | Clock control cell |
-
1971
- 1971-06-04 DE DE19712127944 patent/DE2127944A1/en active Pending
-
1972
- 1972-05-31 GB GB2538872A patent/GB1345464A/en not_active Expired
- 1972-05-31 IT IT2509672A patent/IT956030B/en active
- 1972-06-01 NL NL7207439A patent/NL7207439A/xx unknown
- 1972-06-02 LU LU65452D patent/LU65452A1/xx unknown
- 1972-06-02 BE BE784339A patent/BE784339A/en unknown
- 1972-06-02 FR FR7219898A patent/FR2141744B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2141744B1 (en) | 1973-07-13 |
NL7207439A (en) | 1972-12-06 |
LU65452A1 (en) | 1973-01-22 |
IT956030B (en) | 1973-10-10 |
DE2127944A1 (en) | 1972-12-14 |
FR2141744A1 (en) | 1973-01-26 |
BE784339A (en) | 1972-12-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |