GB1342983A - Waveform storage apparatus and crt displays - Google Patents

Abstract

1342983 Cathode-ray tube displays HONEYWELL Inc 25 May 1971 [15 June 1970] 16765/71 Heading H4T [Also in Division G4] To produce a continuous display of a non- repetitive analogue signal on a cathode-ray tube the signal is converted to digital form in an A/D converter 7 (Fig. 1), the resulting digital signals S1-S6 are circulated in a memory 9 from which output digital signals B1-B6 are derived, converted to analogue form in converter 10 and compared with the Y sweep signal in a comparator 11 which produces, on equality of the two inputs, a beam bright-up pulse via a circuit 13. The converter 7 and the recirculating memory 9 are controlled by a timing control system 8 (also Fig. 2, not shown) which has manually operable means for selectively controlling the operation of memory 9 such that each successive digital signal replaces the oldest digital signal in the memory so that the trace "travels" across the display screen 5 or, alternatively, newly occurring digital signals are not placed in the memory so that the display consists of a "frozen" record of the trace. The analogue-to-digital converter 7 comprises a comparator 30 (Fig. 3) which compares the analogue input with a staircase waveform and produces, on equality of the two inputs, a "low" output which disables a NAND gate 32 to interrupt the supply of clock pulses CK to the flip-flops 36-41 so that the binary count 6 remaining constitutes the required digital value at outputs S1-S6. The staircase waveform is initiated by a timing signal T1 going "low" which resets the flip-flops 36-41 and by rendering transistor 35 conductive discharges a capacitor 34. When, subsequently, T1 goes "high", transistor 35 becomes non-conductive, flip-flops 36-41 commence counting and capacitor 34 commences charging until its level coincides with the level of the analogue input when NAND gate 32 interrupts the clock pulses to the flip-flops and to the amplifier 33 in the staircase waveform generator circuit. The recirculating memory 9 and the D/A converter 10 are described with reference to Figs. 4 and 5 (neither shown).