GB1327283A - Data handling employing time modulation - Google Patents

Abstract

1327283 Multiplex pulse signalling ADEC CORP 22 Sept 1970 [29 Sept 1969] 45117/70 Heading H4L [Also in Division G4] Signals from tranducers 10 to 10n, Fig. 1, are supplied to time modulators 12 to 12n in which the period of a multivibrator output is varied in accordance with the input signal, Fig. 2 (not shown). The outputs of the modulators are combined in time division multiplex on lead 18 via switches 14 to 14n under the control of sequential addressers 16 to 16n operated by address and reset pulses from control 20 over lines 22 and 24 respectively. Initially all the switches are opened by the reset pulse and an address pulse is supplied to cause addresser 16 to close the switch 14. A counter in address control 20, Fig. 6 (not shown) then counts a predetermined number, e.g. ten, of the data pulse signals passing through switch 14 after which a second address pulse is sent out to open switch 14 and close switch 14a. This second address pulse, which is fed to all the sequential addressers, causes addresser 16 to send a signal to the addresser 16a which in combination with the address pulse causes switch 14a to close and the address control 20 now counts ten of the data pulse signals on the second channel. This sequence is repeated until all the switches have been operated and a fresh cycle begins. The address pulses thus are generated at intervals dependent upon the durations of the data pulse signals on the respective channels. The address control 20 co-operates with a digital translator 21, Fig. 6 (not shown) which includes a crystal oscillator producing clock pulses which are gated for the periods of operation of switches 14...14n respectively, to provide corresponding pulse counts which are supplied to display units. The frequency of the clock pulses may be varied to provide different levels of resolution. If the data is to be transmitted to a remote station a remote address control 200 and a digital translator 206 are provided, the digital translator 21 being dispensed with. Operation of the start button at the remote control 200 will cause address control 20 to operate as described. An alternative pulse period modulator, Fig. 8, comprises a capaciter 208 linearly charged via a circuit 212 from a source 210 until a unijunction transistor 214 is triggered. Voltage V IN is controlled by the analogue voltage which thus controls the charging time of the capacitor and the output of the transistor controls a bi-stable flip-flop 219 providing a duration modulated square wave output with symmetrical half cycles.