DE2047870B2 - Data processing system working with time modulation - Google Patents

Description

The invention relates to a device and a method for modulation and complex processing a number of analog signals, such as those from converters to detect certain states or Conditions to be delivered.

The collection, processing and transmission of data and other types of information is a fundamental one Problem that has been expanded and studied intensively for many years. Usually the data picked up by a transducer, modulated onto a carrier and sent to a remote one via wire or radio Place where they are demodulated and evaluated.

Fluctuations in signal size and the noise on transmission lines forced systems that use one Avoid changing the amplitude. The transmission of analog signals with variable amplitude and Systems with pulse amplitude modulation are therefore Hardly used in transmission systems for very precise data processing.

Pulse width modulation systems work with a signal of a fixed frequency and a fixed repetition rate, whose pulse duration 'is modulated as a function of the information to be transmitted. At a In such a system, the duration of a portion of a fixed time interval cycle varies as a function of the information to be transmitted. Yet there is considerable dead time to deal with the size of the signal to be transmitted changes and that of the impressed, fixed repetition rate at Pulse width modulation method is needed.

The invention is based on the object of creating a data processing system in which Data are transmitted as electrical signals in such a way that problems due to fluctuations in signal level are caused and noise is kept as small as possible and idle times or dead times are avoided and nevertheless a modulated signal is provided which can be easily demodulated, with a repeated time-modulated signal is generated and transmitted, the period of which is a measure of the transmitted data, thus reducing the problems associated with amplitude, frequency and pulse width modulation systems or can be reduced.

The invention, in accordance with a preferred embodiment, generates on one of a normal Converter generated state signal a repeatedly fluctuating, modulated signal whose period in has a certain relationship to the detected state The signal comprises a series of temporally contiguous, discrete time images. In particular, the period of the modulated signal, i. H. the time interval between its repetitions, practically linear in relation to that to be processed and transmitted Information (the state being sensed by a transducer). The system is thus from Voltage or signal size fluctuations essentially independent.

In a multi-channel system, for each of the Transmitting analog signals generates a set of repetitively fluctuating or discrete signals each of which has a period or a time image that specifies the analog information to be transmitted in each case. For example, each signal can be a data pulse, the width of which is directly proportional to the analog information. A number of signals of each signal set selected The total duration of this number of signals is used to display the respective analog information

tion signals. As every signal of the sentence is for sirh Hen represents the assigned analog value, the sum or total duration of this number of signals provides a useful arrangement for the average of the information enabled by time modulation. To the complete digitization of the time-modulated signals is a train of clock pulses with a fixed repetition rate for successive gate periods Gate controlled. Each of these gate periods has a duration equal to the total duration of the selected ones Number of signals in the set. For example, if each signal of the set includes a data pulse, its Duration is in an almost linear relationship to the analog input, and if a sentence is ten comprises successive data pulses, the clock pulses are of a fixed repetition rate for the duration controlled by ten of these data pulses via gate circuit, the Hen an analogngrn signals representative channel happened. The clock pulses are then (for processing the next channel information) controlled via gate circuits for a total time which is equal to the total duration of for example ten data pulses of the next channel for processing a further analog signal. By having the fixed repetition rate clock pulse gate equal in time to a whole in this way If the data pulse duration is multiples, one obtains a wide sampling of the time-modulated signal if you work with a smaller period of time, it still contains the same precise information, because the time of the modulated signal runs linearly to the information to be transmitted in all points.

If the sampling by the multiplexer takes place during a period of time that is in direct proportion for the amplitude of the processed information, the multiplexer does not have to move from one to the other at a fixed rate switch to the next channel, but can effectively switch to a subsequent channel, immediately after the end of the fluctuating sampling time of the previous channel.

In the drawing shows

F i g. 1 is a block diagram of a preferred embodiment,

F i g. 2 is a circuit diagram of a converter, time modulator and a multiplex switch of a single channel of the illustrated system,

F i g. 3 a synchronous representation of certain waves (impulses) in the circuit according to FIG. 1 and 2 appear,

F i g. 4 the practically linear assignment of the data, jignal period to the input information to be transmitted,

Fig. 5 is a block diagram of two channels of the Sequence addresser according to FIG. 1,

Fig. 6 further details of the address control and the digital converter according to FIG. 1,

F i g. 7 shows a synchronous representation of further wave (pulse) forms and the tuning, especially in connection with the details of FIG. 6,

F i g. 8 shows an alternative that can be used in the invention Time modulator and

F i g. 9 further details of the decade counter and the associated logic circuit.

According to FIG. 1 comprises the first of several channels of information exchange, processing and processing Modulation circuit comprises a practically normal transducer 10 which is responsive to a condition to be detected and an analog signal output for a time modulus

Lator 12 causes, in turn, via a multiplex switch 14, controlled by a sequence addresser 16, a time-modulated data signal on an output data line 18 causes.

The second and further channels of the information processing system contain practically identical ones Wall arrangements 10a, 10n, the time modulators 12a, 12/1 feed and further multiplex switches 14a and 14/7 feed, which are from the sequence addressers 16a and 16n of the individual channels are controlled. As a result i < > The output data line 18 receives sequentially from the channels each of the time-modulated signals whose Periods are directly proportional to the converter input, as will be explained below.

The data signal on line 18 arrives at r, Address controller 20, the address and reset pulses on lines 22 and 24 to the subsequent

20 comprises, together with the multiplex switches and the sequence addressers of the various channels> n, a multiplex arrangement which uses the reset pulse on line 24 for zero or to initiate a new multiplex cycle, the address pulse on line 22 switching the multiplexer from one to the other channel causes. 2;

The address pulse reaches the sequence addresser 16 from channel 1, which then closes the multiplex switch 14, ie causes this switch to send a data signal to the output data line 18 (all other multiplex switches were previously opened by a reset pulse on line 24). The spacing of the address pulses on line 22 depends on the period of the data pulse signals which come from line 18 to the address control. The latter counts the pulses of a data channel and after a y excluded, dialed number, about ten data pulses are counted, a second address pulse is delivered, causing the indexing of the multiplexer from the channel 1 to the channel. 2 When this second address pulse occurs, which reaches all sequence addressers via a common line 22, the sequence addresser 16 of the first channel opens its multiplex switch 14 and at the same time emits an output transfer signal on the line 26 which, together with the address pulse on the line 22, is sent to FIG j is given to the next sequence addresser 16a. When a pulse is received on the two lines 22 and 26, the addresser 16a closes the multiplex switch 14 for the second channel, modulated data pulses being transferred from this channel to the data output line 18. The address control 20 counts these pulses and, after counting a certain number of data pulses, emits the next address pulse which is received by the sequence addresser 16a from the next channel on the line together with an output on the transfer output line 26a. This sequence continues until all multiplex switches of the channels have been activated at their time and the last channel, the channel π in FIG. 1, is addressed and has supplied its data. At this point in time, the address control determines that a complete cycle of the system has been completed is whereupon a new reset pulse is given to all addressers of the channels to open all multiplex switches via line 24 and the device begins a new cycle

Details of one pass and one pass of the address control and multiplexers are in the following with reference to FIG. 6 and the synchronous representation of FIG. 7 described. To the, Facilitating the description and understanding of how the system works is called Example of a channel according to FIGS. 2 to 5 explained.

In Fig. 2 shows a time modulator and multiplexer switch which is constructed so that it can operate without can be attached to the different types of transducers. A major advantage of the invention is because it can be used with a wide variety of transducers, including those for measuring pressure, temperature, displacements, magnetic or electrical signals, current, voltage, Resistance, etc. Most converters provide an output signal with a voltage or current value, which is in a known relationship to the input state and are therefore with the invention

C ...- »« FM ........ .M MrJl. r »_ DnI 4λ ^ ^ nFnnrlnlltnn Λ · · - Γ · '' · U c · * w% rrf

.jy ^ ittir "* -i" ι, ιιυυαι. t ** - i uvi uuig ^ dii.iiit.11 / lujt um ungj form, the analog output of the converter modulates an oscillator, which supplies a digital signal type in the form of a series of directly abutting, consecutive pulses, the duration of which depends on the input state detected by the converter is assigned linearly.

Fig. 2 shows a linear potentiometer 28 with a resistor section 30 and a transducer Sliding contact 32. The converter is reduced via line 34 from a low-resistance power source Voltage, for example 10 volts, fed at the output of a functional amplifier 36 (in the figure right) is available. The amplifier 36 is via a line 38, for example with a DC voltage of 20 volts, fed via a voltage divider circuit with resistors 40 and 42. The outcome of the Amplifier 36 provides not only for the converter 10, but for all other circuit elements in Fig. 2 shows a low-resistance voltage source, the voltage value of which corresponds to the resistance ratio of the voltage divider is directly proportional and its value of course depends on the DC voltage at the Line 38 depends directly.

After switching on, the 20 volt voltage on line 38 causes a current through resistors 40 and 42 and a Zener diode 44, which has a fixed voltage drop of approx. + 5.6VoIt and thereby holding the line 46 at this value with respect to ground.

An analog voltage signal is generated at the sliding contact 32 of the converter, the magnitude of which (within the Linearity of the transducer) is directly proportional to the position of the sliding contact on the resistor. This analog converter output signal is passed through an impedance matching circuit to be described later and a modulator isolation amplifier 73, which is practically the same as amplifier 36, and does so Control potential signal for the time modulator oscillator.

The oscillator of this time modulator is a modified, free-running multivibrator with two npn transistors 48 and 50 and with timing capacitors 52 and 54, the criss-cross base and collector of the Connect transistors 48 and 50. Two pnp transistors 56 and 58 serve as linear charging current sources for capacitors 52 and 54 and are connected to the Collector on the respective capacitor and with the emitter via resistors 60 and 62 to the 20 volt voltage connected.

The base of transistors 56 and 58 is across a Diode 64 on the low-resistance 10 volt voltage

source at the output of amplifier 36. Since the base-emitter voltage of transistors 56 and 58 is approx. + 0.65VoIt and is therefore equal to the voltage between the cathode and anode of the diode 64, the Emitter of these normally conducting transistors at the same level as the output of the amplifier 36 held, which is the reference voltage for the circuit according to FIG. 2 supplies.

The timing for each half-wave of the symmetrical, astable multivibrator is by two pnp transistors 66 and 68 causes their base in common with the output of the isolation amplifier 73 is connected, at which a proportional version of the transducer output occurs on sliding contact 32. the Transistors 66 and 68 are connected to the emitter via resistors 70 and 72 to the positive voltage of the Line 38 connected.

The transistors are

siti collector yerb ^iinr ^ ' ⁱ n

51 block, the collector current of transistor 58 flows into the capacitor 54 and contains it linearly.

This linear discharge of capacitor 54, which is the potential on the right side of this capacitor, like in Fig. 2, increases, leads to the potential increase at the base of transistor 50, which will eventually be Switch-on potential of approx. + 0.5VoIt compared to the Emitter reached. The for this discharge of the capacitor 54 through the collector current of the transistor 58 The time required is determined from the initial charge on the capacitor 54 and the size of the discharge current via the collector of transistor 58:

are via an RC parallel connection with a Resistor 74 and a capacitor 76 to ground. > <> For timing control, the emitter of transistors 66 and 68 is each connected to one side of capacitor 54 or 52 connected, whereby the voltage value to which these capacitors can be charged, from the Voltage at the respective emitter is controlled. > ϊ

The modified and modulatable, free-running multivibrator is an oscillator which, at its output, the collector of transistor 50, a square wave (83 or 85 or 87, etc. in Fig. 3) supplies, whose both half-waves equally in direct proportion to the input control voltage at the base with each other connected transistors 66 and 68 can be varied. One can thus either positive or negative Half-wave or any whole oscillation as the modulated signal or the data pulse of this r, View time modulator. The basic period of the multivibrator is primarily determined by the size of the Capacitors 52 and 54, the collector current supplied via transistors 56 and 58 and that of the base of the Transistors 66 and 68 supplied voltage magnitude. The period of the output signal changes directly proportional to the change in the base voltage.

To explain a typical multivibrator oscillation, it is assumed that transistor 48 is initially is on (saturated) and that transistor 50 is off (non-conductive). The transistor 56 conducts and its collector current arrives at the base of transistor 48 and approximately holds its collector open the emitter potential of +5.6 volts of the zener diode 44. The collector potential of transistor 50 rises to the Emitter potential of transistor 68. As the collector potential of transistor 50 increases, the Capacitor 52 through resistor 72 until its charge reaches the clamping potential given by the emitter of transistor 68 is formed. During this time the current through resistor 72 through the emitter-collector path of transistor 68 and through the resistor 74 is routed to ground. The voltage drop caused by this current at the resistor 74 is sufficient to reverse bias a diode 5t placed between the base of transistor 50 and the Capacitor 76 is connected and to block this diode during the remaining part of this half-cycle.

Initially, the base potential of transistor 50 is approximately -5 volts below the emitter potential. This means that at the beginning of this half-cycle there is sufficient bias voltage to further block transistor 50. While transistor 50 and diode T = C

dV

(D

Discharge current,

Discharge time,

capacity to be discharged,

Voltage change during discharge.

With the onset of current conduction from transistor 50, the first half-cycle described above is ended and the second half-wave begins immediately, and the multivibrator immediately switches to its second state is switched. With the onset of conduction of transistor 50, its collector potential decreases. This collector potential is via the capacitor 52 with the base of the transistor 48 in connection, the thereby leading less. Due to its lower conduction, its collector potential increases, the increased potential is coupled to the base of transistor 50 via capacitor 54 and makes it even stronger conductive. This feedback turns off transistor 48 and transistor 50 almost instantly switched on.

It should be remembered that the charge on the capacitor 52, d. H. thus the potential on the right-hand side of the in FIG. 2, had a value determined by the emitter potential of transistor 68. When transistor 48 no longer conducts, the linearly discharged transistor 56 carries its collector current to the capacitor 52 and discharges this capacitor linearly until the left side of the capacitor 52 the required switch-on potential reached at the base of transistor 48 (approx. + 0.5 volts compared to the Emitter).

In addition, the time required for the capacitor 52 to discharge linearly is determined by the Initial charge of the capacitor, which in turn depends on the emitter potential of transistor 68 and the size of the linear discharge current of the transistor 56 is determined according to equation (1).

With the onset of conduction of transistor 48, its collector potential goes down and through the capacitor 54, a negative signal is transmitted to the base of transistor 50, which is now less conductive Due to the reduced conduction of this transistor, a positive potential is created at its collector via the Transfer capacitor 52 and causes a further increased current flow of the transistor 48. One has thus again a feedback effect that saturates transistor 48 and transistor 50 keeps locked

Il

As already indicated, the total time is 7 " ₍ for both halves, the same:

T ₁ = T 1 + T ₂ = C

dV
TZ

₊ C ₅

whereby

T \ - duration of a half-wave of the multivibrator,

Ti = duration of the other half-wave of the multivibrator,

Cm = value of capacitor 52,

Ch = value of capacitor 54,

/ r% = current of transistor 56,

/ r ₅₈ = current from transistor 58.

Since the linear discharge current Ic _{56 is} equal to the linear F.ntladesirom In. and the two voltage changes dV in the numerator of the two expressions on the right-hand side of equation (2) are equal, it follows for the entire duration of the oscillator oscillation:

T ₁ = T ₁ + T ₂ = (C,

+ C ₅₈ ) χ - -,

¹ C

- 'rs * -

These equations are based on an input to the modulator of the frequencies of interest actually has a constant voltage value. Nevertheless, the width (duration) becomes each Half-wave of the oscillator from the base voltage to the transistor 66, 68 at a certain point in time determined practically independent of the relative oscillator frequencies and the size of the change in the Converter output. In this way, the modulator almost instantly shows an image in intervals proportionally the sampled signal and generates a time-proportional pulse.

This allows the pulse duration to be linearly modulated by changing the expression dV in numerators of equation (2). This is achieved by changing the voltage value at the base of transistors 66 and 68. Since the pulse duration of the multivibrator is proportional to the voltage value at the base of transistors 66 and 68 and this value is in turn controlled linearly from the output of converter 28 via amplifier 73, the pulse duration at the oscillator output changes proportionally and linearly with the change in the converter output. This assignment is shown in FIG. 4 shown

The oscillator output reaches the base of a pnp transistor 78 whose collector is connected to ground and whose emitter is connected to the positive voltage via a resistor 80. This transistor works as an emitter follower and feeds the multiplex switch of this channel, which is time-modulated depending on the converter (vgL F i g. 5). It can be seen that a time-modulated signal occurs here at the output of the oscillator and at the emitter of transistor 78 (83 in Fig. 3 \ The output comprises a series of square waves with half waves of equal duration, each of which is equal to the duration f _xl , ie directly proportional to the output of the converter of channel 1 changes according to the converter output or control another converter to another state, as in the converter channel 2 in the case

so the data output at the emitter of transistor 78 of the assigned channel assumes the waveform indicated at 85 in FIG. The modulator output in this case comprises a series of square waves with the same half-waves, indicated by the duration t _x i , which in turn are linearly proportional to the state monitored by this converter in this second channel.

It can be seen from this that the assignment between the output of a channel and that of this Channel converter controlled phenomenon like in Fig.4 The linear relationship shown follows. The data signal supplied by the oscillator comprises a repetitive Fluctuating, modulated signal, the period of which is linear to the size of the input signal for this channel assigned. The output of each modulator is a set or series of discrete pulse signals. These Signals are generated in sets of consecutive pulses, one of which is a consecutive pulse group can be scanned, for example by actuating the multiplex switch 14, whereby the desired Information got out of the individual channels.

When the sliding contact on the potenticmeter resistor 30 goes from one end to the other, at a given load, the transducer output has a source with changing impedance. A Voltage divider with resistors 82 and 84 forms a fixed load for the converter output on Sliding contact 32 and represents the input for the isolation amplifier 73. The combination of solid Load and changing transducer source impedance lead to undesired nicliiliiieäriiäi des Converter output. The amount of this non-linearity is proportional to the change in source impedance im Comparison to load impedance.

In order to avoid any load on the transducer sliding contact, the entire for the load required electricity supplied from another source. This is achieved by using complementary transistors 86, 88 and the associated circuit. A voltage dividing effect is provided by a diode 90 of two Transistors 92 and 94, the emitter of the pnp transistor 86 via a resistor Ϊ6 with this voltage divider is connected. The purpose of the voltage divider is to reduce the base-emitter voltage drop! at transistor 86, to avoid about 0.65VoIt and to achieve a minimum current in the resistor 96 when the sliding contact 32 of the converter is in its The upper end position is located and the voltage of the line 34 is detected. The base of the transistor 86 is direct connected to the sliding contact. The voltage at the base and at the emitter of this transistor changes as a direct function of the converter output. The collector of transistor 86 is through a diode 98 and a resistor 100 is connected to ground and is also connected to the base of an npn transistor 88 directly in connection.

The emitter of the latter is connected to ground via a resistor 102, while its collector is connected to a Feedback arrangement with the lower end of the voltage divider made up of resistors 82 and 84 in Connection is and is also connected to the base of transistor 86 directly.

For the purpose of operation it is assumed that the input on the converter causes the voltage on the Sliding contact increases The current through the load resistors 82, 84 decreases proportionally because the This reduces voltage across these resistors

transistor 86 conducts, one pnp transistor less, and the base of transistor 88 goes down. This npn transistor therefore also conducts less. This small reduction in the collector current of the transistor 88 compensates for the reduction in the load current, and is approximately the same as that which otherwise flows through it when the sliding contact goes up.Thus, less current reaches the base of the transistor 86 and a positive feedback current is actually the same in magnitude the load current achieved. This appears as an increase in load impedance and ensures a linear transducer output at the load at every setting of transducer 28.

The silrom through transistor 86 is determined by the value of a resistor 96. The converter output voltage causes a voltage drop IR across resistor 100 in the collector circuit of transistor 86 and a fixed voltage drop across diode 98. Since the base of transistor 88 is connected to the anode of diode 98 and the base-emitter voltage drop is equal to the voltage drop across the diode, the voltage across the resistor 100 is also equal to the voltage drop across the emitter resistor 102 of the transistor 88. By choosing the resistance values of the resistors 96, 100 and 102 accordingly, the collector current of the transistor is determined 88 for the load equal to the current taken from the converter to be supplied to the load, so that the current zero is obtained for each setting of the converter sliding contact 32 on the sliding contact

The output of a converter when fed from any voltage source is determined by the Voltage across its resistance element. The supply voltage must of course be known and used Achieving useful values are kept practically constant.

Alternately, fluctuations in the supply voltage must therefore be compensated for. Usually you need a regulated and stable power supply for truly proportional measurements. The time modulator circuit according to FIG. 2 fulfills this function without regulating the main power supply and causes an output pulse duration exactly proportional to the converter setting. The output pulse duration is as in the Circuit according to FIG. 2 follows, practically insensitive to normal fluctuations in the power supply.

If, for example, the power supply of the circuit decreases from + 20VoIt by a certain value, the low-resistance reference voltage (10 V) at the output of the amplifier 36 decreases by a proportional amount due to the voltage dividing effect of the resistors 40 and 42 and the voltage follow-up effect of the amplifier 36. Since the output of the amplifier is the source of the converter excitation voltage, the size of the converter voltage output is reduced by an equal amount. The clamp voltage magnitude of base connected transistors 66 and 68 which determine the ultimate charge on capacitors 54 and 52 is also decreased by the same amount as the reference magnitude at the output of amplifier 36. This would reduce the pulse duration with a constant capacitor current (see equation [1 J). However, the voltage for the emitter resistors 60 and 62 of the linear charging circuit of the transistors 56 and 58 is reduced by the same percentage. This also reduces the charging current for the timing capacitors 52 and 54 by the same percentage,

so that the fluctuation in the power supply does not cause the output period to change are shown in the following equation:

T C ₅₂ dV dV I. J - «60 τ - dV

T = C ₅₂ R ₁

Since Cs2 and / J »do not change with fluctuations in the power supply, the output pulse duration is independent of such voltage fluctuations.
It can also be seen that the use of the

μ the same reference voltage for feeding the converter and for controlling the voltage control of the multivibrator timing (controlled by transistors 66 and 68) causes an initial change in the output signal as a result of a fluctuation in the reference voltage same voltage fluctuation is changed so that the total period remains the same
The sequence addresser, of which two channels are shown in FIG. Thus, a connection required for a single converter contains the entire circuit according to FIG. 2 with the exception of the converter and, in addition, the sequence addresser according to FIG. 5, everything being arranged in one structural unit which is connected at one end to the converter and at the other end together with other converter and data preparation channels with a common address control, as shown at 20 in FIG. 1 is indicated. Variations with respect to the structural unit, the number of channels and the type of transducer used can be influenced and selected within the scope of the invention while adapting to the respective use.

Each channel of the sequence addresser is the same as the other, with the exception of a single aspect in the first channel to be described. The addresser includes two adjustable and resettable flip-flops 104 and 106, both initially by a pulse from a NAND gate 108 turned back. The latter is a normal, inverting coincidence circuit that delivers a small output signal when two upshifted inputs are received on the input side. If the two upshifted input signals are not coincident, the gate delivers an upshifted output signal. Functionally, a gate for receiving the reset pulses coming to the sequence addresser for a channel is not required, but it is used in this arrangement since a circuit with a number of identical NAND gates and flip-flop circuits is readily available.

An upshifted pulse 241 (FIG. 3) on the reset line 24 from the address controller 20 (see FIG. 1) passes the NAND gate 108 and resets both flip-flop circuits 106 and 104 , with a second NAND gate 110 a small one Receipt from

Output of the RS (reset) side of the flip-flop circuit 104 receives, but receives an upshifted output from its connection to the S (Ste! L) side of the flip-flop circuit 106. This gives an address output transistor 112, the base of which has a resistance coupled to the output of NAND gate 110, has an upshifted signal and therefore conducts.

The collector of transistor 112 is across the line 114 and the resistor 116 (Fig.2) connected to the power supply of 20VoIt. The multiplex switch 14 comprises a field effect transistor (FET), its drain and source electrodes are connected to the data line 18 and the emitter of the transistor 78 are, while its gate electrode is biased via a resistor 119 and via a diode 118 with a read command line 114 is connected when the transistor 112 is switched as a result of the high Output of the NAND gate 110 conducts, the diode 118 is forward-biased and the collector current of the transistor 112 causes a voltage drop across the resistors 116 and 119, which with the Gate electrode of the field effect transistor (FET) 14 are connected, which is thereby turned off. if with all sequence addresser flip-flops reset in this state, all multiplex switches 14 through 14n are open (which are FET switches switched off), so that no data is transmitted to the data line 18.

After the reset pulse, a first address pulse 221 (Fig.3) is on line 22 from the Address control 20 is fed jointly to all sequence addressers of all channels only in channel 1 ier address pulse arrives at both inputs of a third NAND gate 120, which is thus a small one If the flip-flop 104 is set, its output to the NAND gate 110 is switched high (Fig.3) and this as the second Input leads the held and switched-up output from flip-flop 106, this NAND gate is now a small output to the base of transistor 112, so that it no longer conducts Transistor 112 comes the cathode of diode 118 to a higher potential and blocks the signal at the Gate electrode of field effect transistor 14 rises to the potential of the source electrode, so that this Transistor conducts. This makes the multiplex switch of the first channel only when receiving the first Address pulse closed, so that data pulses 83 from the output of the time modulator 12 now via the Multiplex switch 14 can be placed on data line 18.

As will be explained in more detail later, the address control continues to count a predetermined number time-modulated periods or data pulses and gives a second after the completion of each such count Address pulse 222 (Fig. 3) on line 22 from. This second address pulse happens that too NAND gate 120, however, has no effect on flip-flop 104, which was already activated by the previous Address pulse has been set or set. The second address pulse is also directly on a fourth NAND gate 122 of the sequence addresser given, which at its second input a receives an upshifted pulse from flip-flop 104 when this is set. As a result of the arrangement of a Time delay consisting of a resistor 124 and a capacitor 126 between the flip-flop 104 and the NAND gate 122 is the upshifted pulse generated by the flip-flop 104 when the flip-flop 104 is set is delivered, as long as not given to the NAND gate 122 until the first address pulse has ended > The output of NAND gate 122 therefore becomes true upon receipt of the second address pulse 222 (small). The flip-flop 106 is then set and the input from this flip-flop to the NAND gate 110 becomes small. As a result, the output of the NAND Gate 110 is switched up, the transistor 112 conducts and the multiplex switch 14 is open and prevents the transmission of further data pulses from channel 1. The two flip-flops 104 and 106 remain set or set until during the following address pulses

is displayed to run through the multiplexer again and controlled by the next reset pulse on line 24.

Upon receipt of the second address pulse, flip-flop 106 is set, causing its reset page

jo (RS). which are connected to the output transfer line 26 is being upshifted. As a result, a large input goes to the second input of the NAND gate 120a to the sequence addresser of Krjial 2. This NAND gate also receives every address pulse from the common address line 22. Channel 2, which is identical for all subsequent channels, receives inputs for its NAND gate 120a on two different lines, once from the output transfer line 26 of the previous channel and to the

jo change from the common address line. Of the Channel 1 sequence addresser is notable for not having an output transfer signal from a other channel, but both inputs from the common address line 22 to its NAND gate

j5 ter 120 get. Except for the different arrangement of the inputs of the NAND gate 120a are the Sequence addressers of channel 2 and the other channels are identical to each other and to the sequence addresser of channel 1. The sequence addressing contains rer of channel 2 flip-flops 104a, 106a, additional NAND gates 108a, 122a and 110a, delay circuits 124a, 126a and an addresser output transistor 112a connected via a read command output line 114a with the diode and the gate electrode of the Multiplex switch 14a of the second channel of the converter time modulator of the data processing system is connected. This will be when receiving the second Address pulse 222 from the address controller 20 and the data pulses 83 from channel 1 then terminates the Data pulses 85 from channel 2 are transmitted via data line 18 to the AdrCoSen control. The latter now counts continues the predetermined number of data pulses 85 and sends the next after each count has been completed Address pulse 223, corresponding to the data

■ -, -, from channel 2 ended and the reading of the data pulses 87 from the next channel is initiated. It will be because of it recalls that the data pulses are time modulated with the period of each pulse from the to transmitted information depends. It follows that

en the sampling or reading time for each channel is in Depending on the address control changes, which counts a certain number of period-modulated data pulses. Although in FIG. 3 for easier Representation only urei channels are shown, one can

t, 3 of course with any executable number Channels are working, the number of which is only determined by practical considerations, such as rerun and the access time for each channel is limited.

The address controller 20 is shown in FIG. 6 and comprises a group of decade counters 128 and an associated logic circuit (see FIG. 9). The counters 12 $ count the data pulses that are received by an AND gate 130 via a pulse shaper 132 and an input amplifier 134, which receives the data pulses on the data line 18 from the various multiplex switches. Several monostable multivibrators 136, 138, 140 and 142 cause delay intervals A, Di. Oj and i2 »(Fig. 7). The address control also includes two pulse shapers or drivers 144 and 146 which provide address and reset pulses on address control output lines 22 and 24.

The address control also contains a shift register 148 for channel identification and a selector 150 for the number of channels. Individuals to be processed Channels are identified by shift register 1148 at all times and the end of one is completed The time delay 142 is signaled multiple times through this process. It also contains the address control Input OR gates 152 and 154.

The address control works together with a digital converter (Fig. 6). The latter includes a crystal oscillator 156 which provides a friction large and precise repetition rate clock pulses 180 (FIG. 7) to an AND gate 158 which controls these pulses for subsequent transfer to a substantially normal memory 159 in a data pulse shift register HK) the c; hte monostable tipper 140 to the time delay forms a Te ^'1 of the digital converter circuit.

The address control and the digital time converter can be fed by the same power supply as the converters and the time modulators The system can work completely automatically and data to a separate computer deliver or be controlled by this.

A large pulse on the start command line 153, on the right in FIG. 6, either manually controlled or automatically by computer, to the OR gate iSI causes an output pulse 243 (FIG. 7) via the pulse shaper and driver stage 146 to the reset line 24, whereby all flip-flops in the Sequeniiadressierern (Fig.5) are reset. The start command also causes a reset command via the OR gate 11514 to the shift register 148 for channel identification, which is thereby set to zero. The start command pulse at the output of the OR gate; rs 152 also reaches trigger circuits or monostable flip-flops 135, 138 and 140 via a diode 156, whereby the time delays D 1, D ₁ and Di are initiated (cf.Fig. 7) . This start time with the introduction of each delay interval is indicated in the drawing as ίο. At t \, at the end of the delay time D \, the monostable tipper 136 sends a signal to the pulse shaper 144 which generates the first "": n address pulse 221 to turn on the multiple "switch 14 in channel I, which now generates data pulses 83 from the first Channel on the data line 18 are given. It can be seen that these data pulses 83 are also used as pulses on the data line 83 according to FIG. 3 and each have a duration I, \ which is directly proportional to the analog information detected by the converter in channel I.

At t), at the end of the delay time Di from the monostable tipper 138, a blocking pulse at the output on the line 156 is canceled, whereby the AND gate 130 is turned on. This gate as well as gate 158 are blocked by the monostable tipper 138 during the interval Di.At time h , the data pulses 83 supplied from channel 1 via the input amplifier 134 and the pulse shaper 132 begin to pass through the switched gate 130, which thereby generates pulses 172 ( 7) for counting by the decade counter 128 provides. These counters (FIG. 9) comprise as many in series

ίο switched decade counter units such as for counting a desired maximum number of data pulses are required. Figures 6 and 9 show 10 * data pulse counts for selection by a count control switch tö3. If necessary, even more decades can be added will be added.

According to FIG. 9, the decade counter contains and its associated logic circuit includes four normal modulo 10 or decade counter circuits 230,232,234 and 236, each with a group of flip-flops to count 10, 100, 1000 and iOOOO. These decadenters count in known way every input pulse and set all flip-flops after receiving every tenth pulse 'back to zero. After counting the last count of each group of 10 counts, each counter delivers low order an output pulse to the input of the next higher order counter. The count zero of each decade counter manifests itself through one Output of its flip-flop for corresponding AND gates 238, 240, 242 and 244. The different Decade counter AND gate outputs are again in AND circuit via gates 246, 248 and 250 and effect the count signal at the end on the various counter select terminals. So if for example for the first order decade, a count of ten the selector switch 163 is located in the in F i g. 9 and an output upshift appears on line 162 when the Counting ten occurs. The output switched up & down is reversed in an inverter 161 that runs at each Counting from 1 to 9 a switching input for the AND gate 158 (Fig. 6) causes gate 158 to turn off every tenth count. The upshifted signal on line 162 is also applied a monostable multivibrator 167 for delivery a positive signal through a diode 169 to the Reset line 166 of all flip-flops from all decade counters. As indicated above, serves this signal also to trigger each time delay device 136, 138 and 140 (Fig. 6) on occurrence the selected last count.

The decade counters cause a gate pulse 164 (FIG. 7) on an output line 162, which is generated by the The first data pulse given to the counter is initiated and ends at the end of the specified Number of counts. The termination of this gate pulse also resets the decade counters. The counters are arranged in this embodiment so that they selectively a count of 10, 100, 1000 or 10,000 deliver. The manually operated counter control shell ter 163 causes the counter to count from 10 Data pulses. This is caused on line 166 via a monostable tipper 167 and a diode 169 a reset pulse that rises when the decade counter is completed, thereby removing all of the flip-flops in the

h> resets the counter and the counter for the next Makes the meter run ready.

The output of the monostable tipper 136 at time U, the end of the delay time Di,

causes a memory transfer pulse 168 and a channel identification change pulse 170 through suitable pulse shaper circuitry (not shown), whereby the transfer pulse 168 causes the transfer of data from the data shift register 160 to the memory 159 and the change pulse 170 causes the channel shift register ID to be shifted to its next count The shift registers are essentially conventional devices that change or update (update) their counts upon receipt of each input pulse, a 170 kn pulse from register 148 and gated clock pulses from AND gate 158 for register 160. .

Many ways are known for identifying the data from individual channels.For example, it is only necessary to note the beginning of each complete multiplexer run and then to provide a counter in the computer processing the data, which is synchronized with the switching from one channel to the next Mi ; .ä readily recognizes that identification signals which designate each of the channels which are currently being scanned at a given point in time are immediately available at the outputs, for example on line 139, of the channel identification shift register.

At time / 2, the end of the delay time Dj, becomes a data shift register reset pulse 174 generated and given to the data shift register 160 so that this is reset to zero and the Register is ready for the next counter run.

The decade counters 128 now continue to count the predetermined number (selected with switch 163) of pulses 173, one count for each pulse 83 on data line 18. After ten of these are stored, the decade counter gate pulse on line 162 stops and the The decade counter is reset to zero. The gate 158 is no longer controlled and all time delays Du D ₁ and D _{3 are} initiated

It can be seen that the total count of the selected number of data pulses accumulated by decade counter 128 controls the occurrence of time U when a new set of delay units is triggered and the system begins to switch to the second channel of the multiplexer.

During the time interval between h and £ 4, when the decade counter gate signal controls the AND gate 158, there is no blocking signal from the output of the monostable tipper 138 on the line 165, so that the high-frequency pulse train of pulses 180 with a fixed repetition rate from the precise crystal-controlled oscillator 156 is passed through the gate and stored by the shift register 160.

When the AND gate 130 is activated at the end of the time delay Dz , the next immediately following and shaped data pulse from the pulse shaper 132 passes the gate 130 as the first of the group of pulses 172 and the decade counter carries out its first count, with the counter output line 162 receiving the gate signal immediately on gate 158. The final decade counter pulse, the tenth pulse, with the selector switch 163 in the position shown, no longer controls gate 158, whereby the output on this gate is lowered and thereby blocks every 1 additional clock pulse input into the data shift register 160. This final decade counter pulse causes the potential on line 166 to rise momentarily, triggering monostable tippers 136, 138 and 140 for the next channel reading
As with the initiation of the reading of the first channel, the reading of the second channel is also controlled by several time delays.After completion of the delay Dy, which begins for the reading of the second channel at time U (cf. the synchronous representation according to FIG. 7 ) a second address pulse 222 is initiated which opens the multiplex switch 14 of the first channel and closes the multiplex switch 14a of the second channel, whereby data pulses from the latter are given to the data line 18.

The data pulses 85 from the second channel have a greater width than the corresponding pulses 83 from channel 1, which in this case indicates that the magnitude of the sensed by transducer 10a State of channel 2 the size dr: from converter 10

2ä in the canal! the detected condition. As already explained in connection with FIG. 3, there is a linear association between the various detected states and the duration of each pulse or each half-wave.

As with the initiation of the operation of channel 1, the data pulses from channel 2 also appear on data line 18 practically at the same time as the start of the second address pulse.? 22, whereas the initiation of gate 165 from channel 2 at time tj

jo begins at the end of the second delay time Di. The decade counter causes the gate signal 165 at its output, which controls the gate 158 so that the latter is no longer blocked by the output of the monostable kipper 138, whereby the clock pulses 180 from

j} Oscillator 156 can pass gate 158 and be detected by the data shift register, which was reset again at time fc after the end of the time delay D3. At time fs, at the end of the second time delay Dy, a second memory transfer pulse 182 and a second channel identification change pulse 184 are effected to transfer the information from the shift register to the memory 159 and to update the channel identification shift register. The latter now supplies an output signal on line 139 which identifies the second channel. Thereafter, at the end of the second interval D3, a second data shift register reset pulse 186 is caused to reset the register 160.

The decade counters 128 now count pulses 173 generated at the output of the AND gate 130. The pulses 173 have the same width as the pulses 172, but the period between the pulses 173 is determined by the period of the data pulses 85 from channel 2. The decade counters count the specified number (ten in the exemplary embodiment) of the data pulses. After the counting is complete, the gate signal on line 162 no longer controls the clock gate 158, so that no further valley pulses are sent to the data shift register and detected there. Simultaneously with the termination of the clock gate pulses, the reset signal on line 166 of the decadence rises; hler on, resets it and initiates the time delay of the monostable multivibrators 136, 138 and 140 again . This is the beginning of the third scanning and display. This

t; Switching from channel to channel runs continuously while the sampling time for each channel is controlled depending on the duration of the time-modulated data pulses. In an arrangement where the

If the decade counter is set to ten pulses, the sampling time for each channel is practically the same as the total of ten consecutive periods of the individual data signal. The scanning time for channel 1 begins at / j and ends at U , a total time equal to ten times the width of each whole oscillation of the pulses 83. The scanning line for channel 2 begins at time ti and ends at a time that corresponds to ti in an interval equal to ten times the width of each complete oscillation of the pulses 85 follows.

The number of channel selectors 150 comprises a group of digital switches which together are manually set to identify the number of the last channel of a desired multiplexer run. If z. B. to work with 100 channels of data preparation information and each is during a single channel. The total time required for a complete cycle, including the logic time required for rerun, for time D4 is / V (IO · D _d + D ₂ ) + Da, where N is the total number of channels of a multiplexer cycle.

The individual multiplexer sampling times can be increased for greater resolution of the digitization of the time modulation. In the embodiment described, this can be conveniently achieved by operating the data pulse selector switch 163 in FIG. Simply increasing the sample time increases the number of steps or bits put into data shift register 160 during a particular sample time, which also increases digital resolution. Alternatively, for a given sampling time or a given number of consecutive time-modulated data pulses, the frequency of the

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the selector 150 is set to indicate the number 100 so that when the channel identification shift register 148 reaches the identification count 100, there is a coincidence between the address set in the number of channel selector 150 and the identification code contained in the shift register, so that an output on the Line 188 through comparators (not shown) or comparison circuits in the selector

150 is generated, indicating the scanning of the last channel. The count signal of the last channel, which appears as a pulse 190 (FIG. 7), initiates the time delay Da of the monostable multivibrator 142 . The positive output terminal D 'of the monostable multivibrator 142 passes through the OR gate 154 and provides (las channel ID shift register 148 immediately after the initiation of the time delay Da to zero. At the end of the time delay D wd _t by the positive edge of the output terminal D' and the differentiating effect of capacitor 149 and resistor

151 generates a positive, differentiated impulse. The connection Da of the monostable tipper is always switched up when Da is small and vice versa, a common multivibrator arrangement. The differentiated pulse for restarting caused by the time delay Da triggers a new multiplexer cycle of the following channel scan via the OR gate 152, which runs like the whole cycle already described. During this cycle, the sampling time for each channel changes in accordance with the size of the respective information and the duration of the time-modulated pulses that represent the information processed by these channels. The system starts again when the last channel identified in the channel selector 150 by a manually set number has been scanned. This means that not only the scanning time for different channels is varied, but also the total throughput time

Assuming a mean data pulse with a duration of 100 usec, which means that a modulation period of 100 psec is directly proportional to the mean value of a state to be detected by the converter and that the total range time fluctuation is plus or minus 10%, the time delays can be as follows be chosen so that D2 is in the order of magnitude of 200μ $ εΰ, D ^ in the order of magnitude of 600 usec and D * in the order of magnitude of 1000 usec 10 Dd + ft, where D is the duration of a data pulse from a given

results in a significant increase in digital resolution. It follows that with the arrangement with time modulation, that is, by using the information linearity in the time domain, as is the case with the invention, it is possible to work with a similar part of the frequency spectrum for data transmission as is required for normal frequency modulation, but can deliver the same information content 100 times faster. For example, in a normal frequency modulation system at 10 kHz, a normal digital frequency counter is required to count up to 10,000 one second. On the other hand, in the system according to the invention, in which the mean (midrange) duration of the data pulses is selected so that 10,000 data pulses are generated per second and a repetition rate of the oscillator clock 156 of 10 NiHz is used, the sampling period described would, however, be 10 data pulses scans, enabling 10,000 counts. Ten of these data pulses would require a sampling time of around 1 ms for medium (midrange) values. If an even greater resolution is desired with this arrangement, a clock generator 156 with a clock frequency of 100 MHz, for example, can be selected, 100,000 counts being effected for each sampling of ten data pulses. Such precision and resolution is not possible in normal systems with frequency modulation and also not achievable with a conventional pulse width modulator, since the latter works with a fixed frequency or repetition rate and does not transmit any information between the pulse duration of the periods.Bc, continuous transmission is possible in the system according to the invention . With increasing noise it is only necessary to increase the sampling time.

According to FIG. 1, the digital converter 21 can be connected directly to the address controller 20 and both can be in the vicinity of the different information modulation channels. The connection between the address control and the digital converter on the one hand and the various Data preparation channels, on the other hand, only require the system's ground line (not shown) three additional lines. The first is the data line, the other two are the address and the Reset line. With the arrangement shown of the multiplexer and sequence addresser of each channel in the same package as the modulator and converter of each channel, the number remains Lines for connecting the address control and

of the various channels to a minimum. As already mentioned, regardless of the location of the switch or addresser, significant advantages are achieved by packing the converter and modulator into a single unit to reduce the number of lines with analog voltages to a large extent and by using a common power supply. If the data are to be transmitted to a remote station and their acquisition controlled there, the digital converter 21 can be omitted. A second address controller 200, which is practically the same as the first, is provided separately therefrom, a start line 202 and a data line 204 being present between the separate address controller and the address controller 20. A digital converter 206, which is similar to converter 20, as described in detail in FIG. 6, has the same connections to address controller 200 as were described for connecting converter 21 to address controller 20. With this arrangement, the local digitizer 21 is unnecessary and can be omitted. When working with a separate address control 200, the start signal can be given to an OR gate of this control, which the OR gate 152 according to FIG. 6, the separate address controller 200 delivering a reset pulse on line 202 (at the output of the pulse shaper 146 of the separate address controller) which is applied to the start OR gate 152 of the local address controller 20. The latter then performs the entire multiplexer scan pass, as in FIG. 6 and supplies, via a line 204 (FIG. 6) at the output of the input amplifier 134, the various data pulse sets which are given to the input of the amplifier 134 of the separate address control 200 (after suitable signal size control). In this arrangement, the local address controller 20 does not give a restart signal at the output of the monostable multivibrator 142 , so that the start and the restart only take place under the control of the separate address controller 200.

With this separate control, it is possible to avoid one of the two lines shown for connecting the local address control 20 and the separate address control 200 by means of a suitable logic circuit which detects the absence of data in a predetermined period, such as after the end of a complete multiplexer cycle the case is. If the lack of data is detected, the data transmission line 204 is temporarily connected to the start input of the local address control 20 for receiving the start signal of the separate address control. In this case, the line would temporarily lead signals to start and restart from the separate to local address control and used between these signals for data transmission

It should be remembered that the basic Seek progress of the invention in the use of a repetitively fluctuating signal a period of these repeated fluctuations, which are in an approximately linear relationship with the to The circuit according to FIG. 2 is particularly useful for precise linear assignment between the period of the repeated data pulses and the output signal at the sliding contact 32 of the Converter suitable! In certain cases the converter is not linear or has a transfer function that changes over time or with the age of the transducer. To maintain the linearity between Converter input and time period output in this ■> Case it is only necessary, empirically or in some other way, to determine the special transfer function of the To determine converter. This is stored in the computer that responds to the information and they further processed by the various systems

in was modulated and transmitted. If you have an alternative considers the transfer function of the transducer to be relatively stable and known, a Compensation function or an inverse transfer function can be built into amplifier 73, so that the output of this amplifier is then again strictly linear to the state detected by the converter runs.

To use relatively einfarhpn iinrj njrht very With accurate transducers, the system can maintain a considerably higher level of accuracy that is achieved by the transducers lower quality is not degraded. In this case, each channel is used for information processing and -modulation independently calibrated and the respective calibration of each channel in the data processing computer stored to compensate for the individual data signals supplied by the digital converter.

The circuit according to FIG. 2 shows an arrangement for modulating both half waves of the square wave of the oscillator. The principle of the invention can be

jo can also be used in a system where only one of the is time-modulated in both half-waves of the multivibrator. To in this case according to the invention the two To be able to make half waves of each data pulse exactly symmetrical in their duration is the output of the

J3 modulated half-wave multivibrator of a halving circuit fed, for example to a normal flip-flop, which at the beginning of a multivibrator oscillation is set and reset at the beginning of the next oscillation.

All types with analog output voltage can be used as converters, which in one known relationship with the input state to be detected, and the input of the Amplifier 73 is supplied. Instead of one or both time capacitors 52 and 54 according to FIG you can use one or two capacitive converters, in which the capacitance is directly transferred to the one to be recorded State is modified. With this arrangement, the linear charging current of the circuit is maintained Voltages to which the time capacitors are charged and charged remain fixed and do not change into Dependence on the input signal.

The time modulator circuit shown in FIG. 2 offers advantages with regard to voltage regulation, impedance matching and linearity of the output. However, you can also use a time modulator circuit according to FIG. 8, in which a capacitor 208 is charged from a voltage source 210 via a circuit 212 for linear charging to a voltage at which the capacitor voltage is sufficient to make a double base transistor 214 conductive via a load resistor 216. The double base transistor ignites at a fixed percentage of the voltage on the base electrodes 1 and 2. Since in this circuit for external time modulation, the voltage on the base two electrode 218 of the double base transistor is controlled by the analog input voltage Vm, the capacitor 208 charges linearly wide open. until

its charge is sufficient to ignite the double base transistor. This allows for linear charging required time directly proportional to the input voltage at the base-two electrode of the double base transistor. A input signal from the junction between the base-one of the transistor and resistor 216 goes to a flip-flop 219 which has a square wave output of symmetrical Duration of the half-waves and linear assignment to the input signal voltage supplies that of the base two-electrode of the transistor was supplied.

In the device and the method according to the invention for processing data, a Number of periodically repeatable, modulated signals generated whose period duration is the respective size of the individual analog signals of a group. The periodic signals are generated over a number of

of the following periods sampled and the total duration of a number of sampled periods by a number Clock pulses with a fixed repetition rate are digitized for the entire duration of the sampling time via gates be switched. They not only represent the individual data signals from one of the data group channels with its duration an analog information, but the multiplex circuit is designed so that the Sampling time for a given channel is directly proportional to the integer multiple of the data pulses. the The arrangement according to the invention provides a data signal with a proportional, repeatable and periodic one Output that is linear with respect to time and is addressed in this way locally or from a separate location that one can have stable, extremely precise data acquisition and high resolution modulation receives.

7 Bhitt drawings

Claims (24)

Patent claims: 1. Data processing working with time modulation system with at least one input channel, characterized in that each channel has an analog signal input, responsive to the signal input and a repetitive, having time-modulated signal generating modulation devices, the period of the signal in a predetermined relationship to the analog input, and that means for forwarding the time-modulated signal and for display of the entrance are provided. 2. System according to claim 1, characterized by several identical input channels with devices for forwarding the time-modulated signal of each channel and with multiplexing devices on the Modulation devices of a group of channels respond to the modulated signals of the group of channels one after the other to a common output for all channels. 3. System according to claim: i or Z, characterized in that each channel contains a transducer which responds to a state to be detected and generates the analog input 4. System according to claim 3, characterized in that between the signal period and one of the Converter detected input state there is a linear relationship 5. System according to claim 3 or 4, characterized in that the m xiulated signal a Series of discrete, temporal; of contiguous images of time, which in their uaue. < are practically proportional to the state signal. 6. System according to claim 3 or 4, characterized in that the modulated signal has at least one half-wave whose period the Converter output is proportional 7. System according to the preceding claims, characterized in that the converter and the Modulation device are combined into a single unit, the time modulation of the detected state takes place at the detection point and the line length for transmission of the analog data from the converter to the time modulator is reduced to a minimum 8. System according to any one of the preceding claims, characterized in that each Modulation device comprises two bistable switching devices which have mutually exclusive states, with at least one capacitor being the devices connects and switching the devices off the one causes in the other switching state, and that on Devices that respond to the converter are present, which generate a charging voltage on this capacitor which is practical for the converter output is proportional. 9. System according to one of claims 2 to 7, characterized in that each modulation type m direction has a free-running multivibrator with at least one ÄC element for timing, with devices for generating a practically linear charging circuit for the RC-GWed, with devices for Recording of an input signal from the transducer and with devices responding to the input signal for modifying the toilet element in such a way that the Time control (the timing) of the multivibrator in Is varied depending on the input signal. 10. System according to one of claims 2 to 7, characterized by a free-running multivibrator in each modulation device a first and a second transistor with base, collector and emitter electrode. by a first and second time capacitor connected to the base and collector of the transistors, respectively, through third and fourth Transistors connected to the first and the second capacitance and for them one cause practically linear charging current, through fifth and sixth transistors with collector, emitter and base electrode, the emitter electrodes corresponding to the collector electrodes of the first and second transistor are connected, the collector electrodes in connection with each other stand and the base electrodes are jointly led to the output of the converter, so that the from Converter to the base electrodes of the fifth and sixth transistor conducted signal the voltage controls to which the first and second capacitors are charged, increasing the duration of the two half-waves of the multivibrator period proportional to the size of the output signal from Converter is controlled, and by a switching device in the multiplex device, the output line common between all the channels and the Collector electrode of the first or the second transistor is connected. 11. System according to claim 8, characterized in that each channel has a power supply has to supply both the converter and the devices for generating the charging voltage on the capacitor, with fluctuations in the power supply canceling out fluctuations in the converter and the modulation device cause. 12. System according to claim 8 or 11, characterized by having an amplifier in each channel an output connected to the device for generating a charging voltage on the capacitor is connected and a practically fixed input resistance connected to the converter output possesses, and by responsive to the converter output devices for changing the through the input resistance of the flowing current as a function of fluctuations in the converter output. 13. System according to one of claims 1 to 12, characterized in that the multiplexing device means for switching one channel to the next when a predetermined number of modulated signals from the channel die Multiplex device has happened. 14. System according to claim 11, characterized modulated by signal converters responding to the multiplex devices for digitization Signals that pass through the multiplexing devices one after the other and with devices for generating them a train of clock pulses at a rate or frequency which is considerably greater than the repetition frequency of the modulated signals and through Means synchronized with the multiplexing device for gate control of the clock pulse train for a gate time of each channel of the group which practically equal to at least one whole multiple calculating the period of the modulated signal from the assigned channel 15. System according to claim 14, characterized by adjustable means for counting a selected number of modulated signals in the gate devices, by gate pulse devices, which respond to the adjustable devices and generate a gate pulse, the Duration is determined by the time required to count the selected number, and by a coincidence gate having a first input from the device generating the clock pulse and synchronized with the completion of the gate pulse for actuating the devices for switching from one channel into the next. 16. System according to claim 13, characterized by sequence addressers for actuating the Multiplex devices with a channel switching output and address controls for counting a number of signal periods on the common Men Alisgangsleitung including bodies responsible for the completion of the counting of the number Respond periods and give an address pulse to the sequence addresser, whereby the addresser of the next channel its switching device operated and by means for digitizing signals on the common output line. 17. System according to claim 16, characterized in that the sequence addresser is a first Channel includes devices that respond to a first address signal and the switching device of the first channel close and with devices that respond to a second address signal and the Open the switching device of the first channel and generate a channel switching output signal through Sequence addressers in the other channels with facilities responsive to coincidence an address signal and the channel switching output signal and the sequence addresser of the immediately preceding channel and the switching device for this other channel close and by devices that respond to the address pulse that is received on the receipt of this sequence addresser of the channel switching output of the address the previous channel and open the switching device of this other channel and switch on Generate channel switching output signal for the next channel. 18. System according to claim 16 or 17, characterized by first and second devices of the Address control for effecting delay intervals, which are initiated upon receipt of a start command, by a first pulse shaper which is applied to the first time delay device responds and generates this address pulse, by a second pulse shaper for receiving a Input from the output line common to all channels, through a first AND gate with a first input from the second pulse shaper and a blocking input from the second delay device and with an output through one Decade counter for counting the pulses at the output of the first AND gate and for delivery a clock pulse gate signal for the duration of the count, through a second AND gate with a '-.--, first input of: decade counter clock pulse gate and with a blocking input from the second delay device, by a clock pulse generator with an output for providing a third input for the second AND gate, through a data shift register with an input from the second AND gate, through a channel identification shift register with a channel shift input from the first Delay device, through a number of channel selectors for setting a predetermined number of channels, by means of comparing the number set in the channel selector with the number stored in the channel identification shift register Delivery of a display pulse for the last channel by a third time delay device, the responds to the display pulse of the last channel and by means which respond to the third Respond time delay device and a reset pulse to reset all sequence addressers and the channel identification shift register and to initiate the operation of the first, second and third delay device produce. 19. System according to claim 18, characterized by a fourth delay device for delivery a delay interval that begins when a start command is received, by devices that respond to the fourth delay device and reset the data shift register, by a Memory and means responsive to the first delay device and the transfer of data from the data shift register into memory. 20. A method for operating the system according to any one of the preceding claims, characterized characterized in that successively several sets of discrete signals are generated that the signals corresponding sets have a period indicating a plurality of corresponding analog signals and that the entire duration of a selected number of signals of each set to deliver a time-modulated playback of the analog signals is displayed. 21. The method according to claim 20, characterized in that each of the analog signals it is detected that a data pulse train is generated for each of the analog signals, that the pulse of each The data pulse train has a duration indicative of the magnitude of the corresponding analog signal and that the data pulse trains are ready for delivery of the sets of discrete signals are sequentially sampled. 22. The method according to claim 20 or 21, characterized in that for displaying the entire Duration of a selected number of signals of each set gate control of a train controlled by clock pulses of fixed repetition frequency for subsequent gate periods via gates and that each of the successive gate periods is equal to the duration of a selected one Number of signals from another of the sets is. 23. The method according to claim 20 or 22, characterized in that each of the sets during one Time is generated which depends on the sum of the duration of the specified number of signals in each set. 24. The method .'ach one of claims 20 to 23, characterized in that the sets of discrete signals are digitized and transmitted.