GB1326794A - Stored charge device - Google Patents
Stored charge deviceInfo
- Publication number
- GB1326794A GB1326794A GB3866670A GB3866670A GB1326794A GB 1326794 A GB1326794 A GB 1326794A GB 3866670 A GB3866670 A GB 3866670A GB 3866670 A GB3866670 A GB 3866670A GB 1326794 A GB1326794 A GB 1326794A
- Authority
- GB
- United Kingdom
- Prior art keywords
- insulant
- charge
- film
- metal
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002184 metal Substances 0.000 abstract 6
- 230000004888 barrier function Effects 0.000 abstract 3
- 239000004020 conductor Substances 0.000 abstract 2
- 230000001419 dependent effect Effects 0.000 abstract 2
- 230000001066 destructive effect Effects 0.000 abstract 2
- 150000004767 nitrides Chemical class 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000001514 detection method Methods 0.000 abstract 1
- 238000010894 electron beam technology Methods 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 230000003287 optical effect Effects 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Semiconductor Memories (AREA)
Abstract
1326794 Charge storage memory devices CALIFORNIA INSTITUTE OF TECHNOLOGY 11 Aug 1970 [11 Aug 1969] 38666/70 Heading H1M In a charge storage memory device a metal film 42 is deposited on an insulant substrate 40 and carries a first insulant film 44 of e.g. the oxide or nitride of the metal on which a metal e.g. Al film 46 is deposited. The latter is buried in an insulant film 48, e.g. of the metal oxide or nitride on which an outer metal electrode 50 is deposited; the insulant films 44, 48, not being identical but differing in substance and barrier energy to exhibit differential conductance in dependence on high fields with the thicker insulant having the smaller energy barrier (Fig. 1). Film 46 introduces a deep energy well trapping a large charge with high capture probability, and high voltage pulses between 42 and 50 add or remove electrons on negative or positive polarities, which electrons are retained due to insulant films 44, 48. The buried layer 46 may consist of a discontinuous layer assisting the rapid introduction of charge. The device operates as a two terminal memory. A random recess memory comprises an array of storage devices connected at the intersections of X wires 68 and Y wires 66 to X and Y access switches 62, 64 associated with a pulse generator 67 and a current detector 69 (Fig. 2) the array being deposited on a single insulant substrate with the lower electrode comprising the Y strip conductors overlain by oxidized or nitrided layers, a circular metal layer at intersections, a second insulant layer oxidized or nitrited thereon, and a strip conductor overlaying the insulant (Fig. 3, not shown). For write-in a pulse is applied of sufficient potential for the electrons to traverse the insulant and enter or leave the energy well formed by the buried metal layer so as to store a negative or positive charge; the pulse being derived from a generator between the appropriate X and Y access switches to affect the device situated at intersection while leaving other devices unaffected. For partially destructive readout either polarity pulse is applicable with lesser amplitude and the resultant current flow sensed by current detector 69 in series with the pulse generator; the flow amplitude being dependent (Fig. 4, not shown) on the polarity and charge previously stored. For non destructive readout; the array may be scanned by an optical or electron beam respectively effecting internal photoemission over the insulant film barrier light dependent on the stored charge and controlling the photoernission readout current, or sensing the stored charge surface potential for detection as in a scanning electron microscope.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US84905769A | 1969-08-11 | 1969-08-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1326794A true GB1326794A (en) | 1973-08-15 |
Family
ID=25304961
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1907570A Expired GB1329220A (en) | 1969-08-11 | 1970-04-21 | Stored charge device |
GB3866670A Expired GB1326794A (en) | 1969-08-11 | 1970-08-11 | Stored charge device |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1907570A Expired GB1329220A (en) | 1969-08-11 | 1970-04-21 | Stored charge device |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS4936786B1 (en) |
DE (1) | DE2039955A1 (en) |
FR (1) | FR2058205A1 (en) |
GB (2) | GB1329220A (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3624618A (en) * | 1967-12-14 | 1971-11-30 | Sperry Rand Corp | A high-speed memory array using variable threshold transistors |
DE2125681C2 (en) * | 1971-05-24 | 1982-05-13 | Sperry Corp., 10104 New York, N.Y. | Memory with reduced write-on time - by using bipolar rectangular wave as gate signal for FETs |
ES404185A1 (en) * | 1971-07-06 | 1975-06-01 | Ibm | A cellular disposal of casual access accorded by electric load. (Machine-translation by Google Translate, not legally binding) |
JPS50140737U (en) * | 1974-05-07 | 1975-11-19 | ||
DE2736715C2 (en) * | 1976-08-16 | 1985-03-14 | Ncr Corp., Dayton, Ohio | Random access storage device |
EP0159601A3 (en) * | 1984-04-10 | 1987-08-19 | Hartwig Wolfgang Prof.Dr. Thim | Logic circuit arrangement with appropriately constructed field-effect transistors |
DE69523287D1 (en) * | 1995-03-03 | 2001-11-22 | St Microelectronics Srl | Electrically programmable and erasable non-volatile memory cell and FLASH and EEPROM type memory arrays |
US7602069B2 (en) | 2004-03-31 | 2009-10-13 | Universität Duisburg-Essen | Micro electronic component with electrically accessible metallic clusters |
-
1970
- 1970-04-21 GB GB1907570A patent/GB1329220A/en not_active Expired
- 1970-08-11 FR FR7029473A patent/FR2058205A1/fr not_active Withdrawn
- 1970-08-11 JP JP6980670A patent/JPS4936786B1/ja active Pending
- 1970-08-11 GB GB3866670A patent/GB1326794A/en not_active Expired
- 1970-08-11 DE DE19702039955 patent/DE2039955A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
DE2039955A1 (en) | 1971-02-25 |
GB1329220A (en) | 1973-09-05 |
JPS4936786B1 (en) | 1974-10-03 |
FR2058205A1 (en) | 1971-05-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |