GB1325621A - Frequency band converter - Google Patents

Abstract

1325621 Frequency compression and expansion RAYTHEON CO 21 April 1971 [7 May 1970] 10561/71 Headings H4J and H4R [Also in Division G4] In a frequency band converter in which signals to be compressed or expanded in frequency are entered into storage at a first rate and read out at a second rate, two stores are provided, read out from one taking place while signals are being entered in the other. As described analog speech signals are converted to digital delta modulated form and groups of 400 bits are fed alternately into two 400 bit shift registers. The register currently receiving the signal is stepped at a first frequency equal to the bit frequency while the other register is stepped at half or double that frequency reading out half the previously stored group or that group and a repeat of that group. The output signals which are digital representations of the input signal at half or twice its frequency are integrated to convert to analog form. As shown the converter described above is incorporated at 65 in a diver's telephone equipment to compress voice frequencies distorted by the use of helium into the normal 5 KHZ speech band which is modulated with a 10 KHZ carrier at 66 and transmitted to the surface unit in audio frequency form. At the surface unit the received signals are demodulated at 68 and applied to an earphone or loud-speaker 71. Speech in the opposite direction employs carrier working as shown with frequency compression or expansion. The analogue to digital converter comprises (Fig. 3) a comparator 13 which gives a positive output if an input 21 exceeds a feedback 20 by a fixed amount, gives a negative output if the feedback 20 exceeds the input 21 by the fixed amount and produces no output if the input and feedback differ by less than the predetermined amount. Positive output of the comparator sets a J-K flip-flop at the next clock pulse 26 to give a positive output at 17 driving an inte- grator. When the rising level of the feedback 20 exceeds the input by the predetermined amount the comparator gives a negative output which on the arrival of the next clock pulse resets the flip-flop. The output of the integrator drops until the comparator reverts to positive output and the cycle repeats. The resultant digital output at 18 is a "1" level pulse of duration equal to a number of clock pulse periods proportional to an input signal level separated by single period "0" level signals.