GB1313278A - Line terminator - Google Patents

Abstract

1313278 Non-contact making relays; transistor switching circuits INTERNATIONAL BUSINESS MACHINES CORP 8 Feb 1972 [26 Feb 1971] 5692/72 Headings H3B and H3T A pulse on a line 1, 2, Fig. 1, causes the primary winding 5 of a transformer to be short circuited so that the impedance of the secondary winding 6 drops and the output of an oscillator 25 is coupled to both inputs of an AND (or NAND) gate 23 to trigger it. The primary winding is short circuited by a transistor 3 when line 1, 2 carries a pulse. The oscillator 25 runs continuously but cannot trigger the AND gate when the secondary impedance is high. Consider the oscillator during that part of its cycle when point 50 is at a high potential; if a pulse is received on line 1, 2, this high potential is transmitted via diode 21 directly to the input 16 gate 23 and also via the secondary 6, now of low impedance, to input 15 of the gate. In the other half of the oscillator cycle the high potential at point 59 activates the gate similarly, via diode 22. In Fig. 3 a pair of transistors 3, 42, provide a balanced input to eliminate noise effects, and the oscillator and gate are shown in more detail, the latter here being a NAND gate. The inputs of the latter are biased by resistors 29, 30, and the diodes 21, 22 are reversed with respect to Fig. 1. Consider that part of the oscillator cycle when transistor 13 is non-conductive, and suppose no input occurs on line 1, 2; the input 16 of the NAND gate is at a high potential because it is connected via resistor 30 to a rail +27 and because both secondary 6 and transistor 13 are high impedance. The input 15 is however at a low potential because it is grounded via diode 21 and the conductive transistor 12. If the line 1, 2, is pulsed the secondary winding is of low impedance so that the potential at point 16 also falls thereby removing the bias on the base of the NAND gate transistor 47 and switching the output 24 to a high value. A similar situation occurs during the other half of the oscillator cycle so that the gate output is high when a signal occurs on line 1, 2, and low when the signal is absent.