GB1291575A - Methods and apparatus for the production of semiconductor devices by electron-beam patterning and devices produced thereby - Google Patents

Abstract

1291575 Programmed control TEXAS INSTRUMENTS Ltd 30 June 1970 [3 July 1969] 33555/69 Heading G3N [Also in Division H1] In the manufacture of a semi-conductor device such as an integrated circuit, wherein an oxidecoated silicon wafer coated with a photo-resist is scanned by an electron beam to expose the resist, the wafer is located approximately by visual observation and accurately in response to signals obtained by scanning it with the beam. The wafer may be inscribed with a coarse grid with a pitch of 2À5 mm and a finer grid with a pitch of 250 microns for alignment purposes, Figs.1 and 2 (not shown). In addition each 250 micron square which is to form a semi-conductor cell may be provided with a reference marker cross, Fig. 5 (not shown). The wafer is mounted on a worktable 20, Fig. 4, and aligned with the aid of the coarse grid observed through a mirror 23 and an optical microscope 22. The marker crosses on the centre line of cells are then scanned by the electron beam to produce secondary emission which is amplified by a channel multiplier 24 and fed to a cathode ray display 26 to enable the operator to check the alignment and make any fine adjustment which is necessary. Thereafter 100 cells are exposed in sequence by the electron beam under the control of the punched paper tape reader 31, after which the table 20 is moved mechanically 2À5 mm and the alignment and exposure steps repeated, and so on until the whole wafer has been treated. The output from the tape reader 31 comprises indications of the starting co-ordinates (X 1 Y 1 ) within each cell and of the scan amplitudes (X L Y L ) necessary to expose the required areas. These are converted in pattern generator 27, illustrated in detail in Fig. 6 (not shown) into analogue signals controlling the currents through the deflection coils and into blanking signals which deflect the beam into an inoperative position. The circuits include distortion correction circuits, Fig. 6F (not shown) which add components such as ay<SP>3</SP> and byx<SP>2</SP> to the Y deflection coil, a hysteresis logic circuit, Fig. 6E (not shown) which ensures that stepping signals are applied to the deflection coils in a correct sequence to avoid errors due to magnetic hysteresis, and pattern alignment circuits which allow small shifts in any direction, a small rotation, or a small change in pattern size to be produced by the operator. The sweep rates of the rasters can be adjusted to give the required electronic exposure for the resist being used. An alternative way of marking the wafer comprises inscribing grids of n type material in a p-type wafer and reverse biasing the junction; when scanned by the electron beam, current pulses pass through the junction, Figs.7 and 8 (not shown).