GB1277988A - Low noise level semiconductor device and method of manufacturing same - Google Patents

Low noise level semiconductor device and method of manufacturing same

Info

Publication number
GB1277988A
GB1277988A GB04771/70A GB1477170A GB1277988A GB 1277988 A GB1277988 A GB 1277988A GB 04771/70 A GB04771/70 A GB 04771/70A GB 1477170 A GB1477170 A GB 1477170A GB 1277988 A GB1277988 A GB 1277988A
Authority
GB
United Kingdom
Prior art keywords
layer
dislocation density
emitter region
nitrogen
ethyl silicate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB04771/70A
Inventor
Takatoshi Matsuo
Morio Inoue
Yoichi Okabayashi
Seiki Yamao
Hiroshi Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2402769A external-priority patent/JPS5116311B1/ja
Priority claimed from JP2402869A external-priority patent/JPS5122347B1/ja
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Publication of GB1277988A publication Critical patent/GB1277988A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors

Abstract

1277988 Semi-conductor devices MATSUSHITA ELECTRONICS CORP. 26 March 1970 [28 March 1969 (3)] 14771/70 Heading H1K The noise level in a Si transistor is reduced by providing a dislocation density in the emitter region of less than 10<SP>5</SP> cm.<SP>-2</SP>, and preferably also by arranging the surface concentration of conductivity-determining impurities in the emitter region to be in the range 1 Î 10<SP>19</SP>-5 x 10<SP>20</SP> atoms/cm.<SP>3</SP>. Three embodiments are described, each comprising a planar Si transistor having a B-doped base region diffused either from a B layer deposited from BBr 3 or from a SiO 2 - B 2 O 3 layer deposited by thermal decomposition of ethyl silicate and trimethyl borate. The emitter region may be formed by diffusion of P from a SiO 2 -P 2 O 5 layer containing 1-30% by wt. of P 2 O 5 , e.g. formed by thermal decomposition of the mixed vapours of ethyl silicate and trimethyl phosphate, and cooling the Si body slowly to produce the required low dislocation density. Dislocation density may also be reduced by including in the emitter region an electrically neutral element such as Sn or Ge. This may be achieved by incorporating SnO 2 into the mixed oxide layer which serves as the emitter diffusion source, the layer being sintered at 800‹ C. in oxygen before diffusion takes place at 1050‹ C. in nitrogen. The layer may be deposited from a carrier gas comprising nitrogen and oxygen, the nitrogen having been passed over solutions of ethyl silicate, trimethyl phosphate and tin tetranormalbutyl. In this case a phosphorus surface concentration of as high as 7 x 10<SP>20</SP> atoms/cm.<SP>3</SP> may be tolerated while maintaining the dislocation density below the required limit.
GB04771/70A 1969-03-28 1970-03-26 Low noise level semiconductor device and method of manufacturing same Expired GB1277988A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2402769A JPS5116311B1 (en) 1969-03-28 1969-03-28
JP2402969 1969-03-28
JP2402869A JPS5122347B1 (en) 1969-03-28 1969-03-28

Publications (1)

Publication Number Publication Date
GB1277988A true GB1277988A (en) 1972-06-14

Family

ID=27284487

Family Applications (1)

Application Number Title Priority Date Filing Date
GB04771/70A Expired GB1277988A (en) 1969-03-28 1970-03-26 Low noise level semiconductor device and method of manufacturing same

Country Status (3)

Country Link
DE (1) DE2014903B2 (en)
FR (1) FR2037280B1 (en)
GB (1) GB1277988A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0176409A2 (en) * 1984-09-06 1986-04-02 Fairchild Semiconductor Corporation Cmos circuit having a reduced tendency to latch
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2189876A1 (en) * 1972-06-23 1974-01-25 Anvar Radiation resistant silicon wafers - and solar cells made therefrom for use in space
GB2049643B (en) * 1979-05-30 1983-07-20 Siemens Ag Process for the production of silicon having semiconducting proprties

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3346428A (en) * 1964-02-27 1967-10-10 Matsushita Electronics Corp Method of making semiconductor devices by double diffusion

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0176409A2 (en) * 1984-09-06 1986-04-02 Fairchild Semiconductor Corporation Cmos circuit having a reduced tendency to latch
EP0176409A3 (en) * 1984-09-06 1987-05-06 Fairchild Camera & Instrument Corporation Cmos circuit having a reduced tendency to latch
US4728998A (en) * 1984-09-06 1988-03-01 Fairchild Semiconductor Corporation CMOS circuit having a reduced tendency to latch

Also Published As

Publication number Publication date
FR2037280B1 (en) 1974-10-11
FR2037280A1 (en) 1970-12-31
DE2014903B2 (en) 1973-06-28
DE2014903A1 (en) 1970-10-01

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
746 Register noted 'licences of right' (sect. 46/1977)
PE20 Patent expired after termination of 20 years