GB1262502A - Improvements in or relating to semiconductor devices and methods of making them - Google Patents

Improvements in or relating to semiconductor devices and methods of making them

Info

Publication number
GB1262502A
GB1262502A GB4559971A GB4559971A GB1262502A GB 1262502 A GB1262502 A GB 1262502A GB 4559971 A GB4559971 A GB 4559971A GB 4559971 A GB4559971 A GB 4559971A GB 1262502 A GB1262502 A GB 1262502A
Authority
GB
United Kingdom
Prior art keywords
type
layer
region
diffused
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4559971A
Inventor
Vincent John Glinski
Bernard Thomas Murphy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Priority claimed from GB4859/69A external-priority patent/GB1262501A/en
Publication of GB1262502A publication Critical patent/GB1262502A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
    • H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

1,262,502. Semi-conductor devices. WESTERN ELECTRIC CO. Inc. 29 Jan., 1969 [5 Feb., 1968; 23 Dec., 1968], No. 45599/71. Divided out of 1,262,501. Heading H1K. A semi-conductor circuit element such as the bipolar transistor shown is isolated laterally from the remainder of the wafer, which may contain other transistors-or-circuit elements such as diodes, resistors or capacitors, by a field-effecttype pinching off of a normally conductive channel in a.layer 242 due to reverse biasing of two PN-junctions parallel to the wafer surface and on either side of the layer 242. The unshaded portions of Fig. 23 represent the depletion regions associated with the various junctions under reverse bias. The structure is formed by epitaxial deposition of an N-type layer 242 on a P-type Si substrate and subsequent formation by epitaxy, duffusion or ion implantation of a P-type layer on the layer 242. Localized N+ type regions 246, 247, the latter surrounding the former, are formed by selective diffusion or ion implantation, :a passivating layer, e.g. of silicon oxide or nitride, aluminium oxide, zirconium oxide or comprising multiple layers, is formed and electrodes are provided as shown. The N-type layer 242 is of relatively high resistivity, so when the parallel junctions are reverse biased the depletion regions extend mainly into the layer 242 and pinch it off in a zone surrounding the collector region of the transistor. In other embodiments the pinch-off effect occurs in an N-type channel between the P-type substrate and a P-type region (144), Fig. 14 (not shown), diffused or ion implanted into an N-type epitaxial layer (142). The P-type region (144) in this case surrounds a portion of the layer (142) which constitutes the collector region of the transistor, the base, emitter and collector contact regions being provided by selective diffusion or ion implantation within the surrounded portion. A silicon oxide mask may be used to define the diffused regions, a mask of gold or platinum being used if ion implantation is employed. Embodiments are described in which an N-type epitaxial layer (47), Fig. 10 (not shown), is formed on a P-type substrate (40) and an annular N+ type zone (48) is selectively diffused or implanted therein to form a collector contact region extending down towards or into a buried N+ type zone which lies between the P-type substrate and the N-type epitaxial layer (47). A P-type dopant is then diffused or implanted non-selectively into the entire surface of the epitaxial layer so that the surface of the N + collector contact zone (48) is not converted to P-type conductivity due to its high N-type impurity content, but the remainder of a surface layer of the N-type layer (47) is converted. A P-type base region is thus formed inside the annular N+ type region (48), and a surrounding P-type surface layer (50) is also thus provided. An N+ emitter region is diffused or implanted into the base region. Field-effect isolation of the transistor is then provided by reverse biasing of the two back-toback junctions between the substrate (40) and the epitaxial layer (47) and between the layer (47) and the P-type surface layer (50) so that the remaining N-type channel through the layer (47) is pinched off. Boron, phosphorus, arsenic and antimony are referred to as suitable dopants for the various regions. Contact thereto may be made by means of a beam-lead technique.
GB4559971A 1968-02-05 1969-01-29 Improvements in or relating to semiconductor devices and methods of making them Expired GB1262502A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US70316568A 1968-02-05 1968-02-05
US78634568A 1968-12-23 1968-12-23
GB4859/69A GB1262501A (en) 1968-02-05 1969-01-29 Semiconductor devices and methods of making them

Publications (1)

Publication Number Publication Date
GB1262502A true GB1262502A (en) 1972-02-02

Family

ID=27254512

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4559971A Expired GB1262502A (en) 1968-02-05 1969-01-29 Improvements in or relating to semiconductor devices and methods of making them

Country Status (1)

Country Link
GB (1) GB1262502A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0603437A1 (en) * 1992-09-02 1994-06-29 Motorola, Inc. Semiconductor device having reduced parasitic capacitance and method of fabrication
WO2016018774A1 (en) * 2014-07-30 2016-02-04 Qualcomm Incorporated Biasing a silicon-on-insulator (soi) substrate to enhance a depletion region

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0603437A1 (en) * 1992-09-02 1994-06-29 Motorola, Inc. Semiconductor device having reduced parasitic capacitance and method of fabrication
SG85053A1 (en) * 1992-09-02 2001-12-19 Motorola Inc Semiconductor device and method of formation
WO2016018774A1 (en) * 2014-07-30 2016-02-04 Qualcomm Incorporated Biasing a silicon-on-insulator (soi) substrate to enhance a depletion region

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