GB1260347A - Demodulators - Google Patents
DemodulatorsInfo
- Publication number
- GB1260347A GB1260347A GB4590569A GB4590569A GB1260347A GB 1260347 A GB1260347 A GB 1260347A GB 4590569 A GB4590569 A GB 4590569A GB 4590569 A GB4590569 A GB 4590569A GB 1260347 A GB1260347 A GB 1260347A
- Authority
- GB
- United Kingdom
- Prior art keywords
- output
- multiplier
- input
- envelope detector
- detector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D1/00—Demodulation of amplitude-modulated oscillations
- H03D1/22—Homodyne or synchrodyne circuits
- H03D1/24—Homodyne or synchrodyne circuits for demodulation of signals wherein one sideband or the carrier has been wholly or partially suppressed
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
1,260,347. Detector circuits. BRITISH BROADCASTING CORP.. 12 Aug., 1970 [17 Sept., 1969], No. 45905/69. Heading H3Q. A demodulator comprises an envelope detector and multiplying means connected in series between an input and output, and a phase detector connected between the input and the multiplying means, which is arranged to multiply the signal in the series circuit by a sinusoidal function of the output of the phase detector, or by an approximation thereto. The arrangement is particularly suitable for demodulating amplitude-modulated carriers with asymmetrical sidebands. In one embodiment, the signal to be demodulated is fed from terminal 10, Fig. 1 to envelope detector 11, the output of which is fed to multiplier 16 and also to subtraction circuit 17. Signal from terminal 10 is also fed via limiter 12 to a phase discriminator comprising frequency discriminator 13 and integrator 14, the output of which is squared in squarer 15 and forms the second input to multiplier 16. The output from multiplier 16 forms the second input to subtraction circuit 17, in which it is subtracted from the input from envelope detector 11. In a second embodiment, the incoming signal is applied directly to the multiplier and subtraction circuit, and the envelope detector is connected between the latter and the output terminal (Fig. 2, not shown). In a further embodiment, the integrator 14, Fig. 3 provides two outputs of opposite polarity, to each of which is added a constant voltage in unit 22, the two outputs of which are applied, together with the output from envelope detector 11, to multiplier 23.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4590569A GB1260347A (en) | 1969-09-17 | 1969-09-17 | Demodulators |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB4590569A GB1260347A (en) | 1969-09-17 | 1969-09-17 | Demodulators |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1260347A true GB1260347A (en) | 1972-01-12 |
Family
ID=10439051
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB4590569A Expired GB1260347A (en) | 1969-09-17 | 1969-09-17 | Demodulators |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1260347A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991011854A1 (en) * | 1990-01-23 | 1991-08-08 | Ampsys Limited | Amplitude locked loop circuits |
-
1969
- 1969-09-17 GB GB4590569A patent/GB1260347A/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991011854A1 (en) * | 1990-01-23 | 1991-08-08 | Ampsys Limited | Amplitude locked loop circuits |
US5341106A (en) * | 1990-01-23 | 1994-08-23 | The Governors Of Paisley College Of Technology | Amplitude locked loop circuits |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |