GB1259883A - Encapsulated beam lead construction for semiconductor device and assembly and method - Google Patents

Encapsulated beam lead construction for semiconductor device and assembly and method

Info

Publication number
GB1259883A
GB1259883A GB37426/69A GB3742669A GB1259883A GB 1259883 A GB1259883 A GB 1259883A GB 37426/69 A GB37426/69 A GB 37426/69A GB 3742669 A GB3742669 A GB 3742669A GB 1259883 A GB1259883 A GB 1259883A
Authority
GB
United Kingdom
Prior art keywords
layer
silicon
semi
circuit elements
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB37426/69A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Signetics Corp
Original Assignee
Signetics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Signetics Corp filed Critical Signetics Corp
Publication of GB1259883A publication Critical patent/GB1259883A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)

Abstract

1,259,883. Semi-conductor devices. SIGNETICS CORP. 25 July, 1969 [26 July, 1968], No. 37426/69. Heading H1K. A semi-conductor assembly 49 comprises a plurality of circuit elements 29 formed in a body of semi-conductor material and has beam leads 43 connected to the circuit elements, there being a layer 14 of insulating material encapsulating the body. The circuit elements are isolated from one another, in the various embodiments described, by reverse biased PN junctions, air, or solid dielectric material, and from an integrated circuit. The semi-conductor material used is silicon. The method of forming the assembly in the embodiment wherein isolation is provided by reverse biased junctions comprises etching grooves in a wafer of monocrystalline silicon, covering the grooved surface with a layer of silicon dioxide, and growing a support body of polycrystalline silicon over the surface. The monocrystalline silicon is then removed by grinding to expose the polycrystalline silicon at the bottom of the grooves so that islands of monocrystalline silicon are formed in which the circuit elements are provided in conventional manner. Following this a layer 28 of silicon dioxide is grown over the surface and a beam lead construction is formed by etching contact windows 42 in the layer 28 and sputtering platinum over the whole surface to form a platinum silicide layer which is etched away except for the parts 44 in the windows, a layer 46 of titanium is then deposited, followed by a layer 47 of platinum and a final top layer of gold which may have a greater thickness at its outer extremities which form the beam leads than it has elsewhere. Finally the support body of polycrystalline silicon is removed. Silicon nitride and aluminium oxide may also be used as the insulating layer material. Methods of forming assemblies with air and dielectric material isolation are also described.
GB37426/69A 1968-07-26 1969-07-25 Encapsulated beam lead construction for semiconductor device and assembly and method Expired GB1259883A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US74807068A 1968-07-26 1968-07-26

Publications (1)

Publication Number Publication Date
GB1259883A true GB1259883A (en) 1972-01-12

Family

ID=25007867

Family Applications (1)

Application Number Title Priority Date Filing Date
GB37426/69A Expired GB1259883A (en) 1968-07-26 1969-07-25 Encapsulated beam lead construction for semiconductor device and assembly and method

Country Status (4)

Country Link
DE (1) DE1937755A1 (en)
FR (1) FR2014743A1 (en)
GB (1) GB1259883A (en)
NL (1) NL6911479A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599703A (en) * 2020-05-09 2020-08-28 中国电子科技集团公司第十三研究所 Preparation method of beam lead of GaN device or circuit on SiC substrate

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5120267B2 (en) * 1972-05-13 1976-06-23
NL7215200A (en) * 1972-11-10 1974-05-14
US4257061A (en) * 1977-10-17 1981-03-17 John Fluke Mfg. Co., Inc. Thermally isolated monolithic semiconductor die

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111599703A (en) * 2020-05-09 2020-08-28 中国电子科技集团公司第十三研究所 Preparation method of beam lead of GaN device or circuit on SiC substrate
CN111599703B (en) * 2020-05-09 2021-09-03 中国电子科技集团公司第十三研究所 Preparation method of beam lead of GaN device or circuit on SiC substrate

Also Published As

Publication number Publication date
FR2014743A1 (en) 1970-04-17
NL6911479A (en) 1970-01-28
DE1937755A1 (en) 1970-02-12

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PLNP Patent lapsed through nonpayment of renewal fees