GB1251235A - - Google Patents
Info
- Publication number
- GB1251235A GB1251235A GB1251235DA GB1251235A GB 1251235 A GB1251235 A GB 1251235A GB 1251235D A GB1251235D A GB 1251235DA GB 1251235 A GB1251235 A GB 1251235A
- Authority
- GB
- United Kingdom
- Prior art keywords
- sync
- frequency
- counter
- clock
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/06—Generation of synchronising signals
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
Abstract
1,251,235. Television. TELEMATION Inc. 23 Oct., 1968 [23 Oct., 1967], No. 47387/68. Heading H4F. A television timing pulse generator comprises a clock oscillator the frequency of which is several times greater than twice the line frequency, the leading and trailing edges of all the timing pulses being precisely clock derived by division through digital circuitry to produce the required vertical drive, horizontal drive, composite sync., mixed blanking output pulses, and in colour television burst gate pulses. As shown, Fig. 1, the generator comprises a high frequency clock oscillator 4, preferably crystal controlled, the frequency of which for NTSC standards comprises four times the 3À58 MHz colour subcarrier frequency. The clocking frequency is divided by four in counter 8 to derive the colour subcarrier and divided by seven in counter 6 and fed via a horizontal sync. lock controlled oscillator 26 (see later) to a series of counters 16 comprising divide-by-sixty-five counter 18, divide-by-three counter 20, divideby-seven counter 22, and divide-by-twenty-five counter 24. For monochrome operation the colour section 2 may be replaced by or suitably switched to high-frequency clocking oscillator 28. Multiple output pulses derived from within individual counters 18, 20, 22 and 24 provide logic 32 with accurately clock-timed pulse signals i.e. a plurality of waveforms (Fig. 3, not shown) are passed through separate paths in multiple connections 42, 44 and 46. Logic 3 digitally translates the signals into vertical drive, horizontal drive, composite sync., and mixed blanking waveforms and a burst gate pulse train. The counters of set 16 comprise " JK " flip-flops (Fig. 2, not shown) and the logic 32 comprises a plurality of NOR gates (Figs. 2 and 4, not shown). To lock the output pulses of the synchronizing generator in frequency and in phase with a remote source of composite sync. signal e.g. for creating special effects wherein two or more images are keyed or superimposed to produce a common mixed picture, the high frequency clock pulses from clock 28, Fig. 13, are fed to a phase comparator 430 in sync. lock system 26, together with the continuous pulse-train information from voltage controlled oscillator (VCO) 436 which is also fed to the counter set 16 as in Fig. 1, the output of phase comparator 430 being fed via switch 428 and low-pass filter 434 to control VCO 436. In addition a second phase comparator 438 compares the horizontal pulse train information from a remotely located generator on line 440 with the output of the local sync. generator on line 418, and with switch 448 switched to its sync. lock position 432, the output of the comparator is used to control VCO 436. The low pass filter 434 besides maintaining proper correction voltage at switch 448 during transfer, also limits the time rate of change so as to produce a reduction in the raster disturbance resulting from establishment of horizontal sync. A known sync. lock system (26a, Fig. 12, not shown) may be utilized in which a high frequency clock and VCO is incorporated into the system.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US67728667A | 1967-10-23 | 1967-10-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1251235A true GB1251235A (en) | 1971-10-27 |
Family
ID=24718083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1251235D Expired GB1251235A (en) | 1967-10-23 | 1968-10-23 |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE1804492A1 (en) |
GB (1) | GB1251235A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4410907A (en) * | 1981-11-16 | 1983-10-18 | Rca Corporation | Burst gate keying and back porch clamp pulse generator |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2548831C2 (en) * | 1974-12-20 | 1985-11-14 | Nanometrics Inc., Sunnyvale, Calif. | Pulse generator for raster display devices |
JPS6033030B2 (en) * | 1978-12-23 | 1985-07-31 | ソニー株式会社 | synchronous signal generator |
-
1968
- 1968-10-22 DE DE19681804492 patent/DE1804492A1/en active Pending
- 1968-10-23 GB GB1251235D patent/GB1251235A/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4410907A (en) * | 1981-11-16 | 1983-10-18 | Rca Corporation | Burst gate keying and back porch clamp pulse generator |
Also Published As
Publication number | Publication date |
---|---|
DE1804492A1 (en) | 1970-02-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |