GB1241363A - Improvements to data processing systems duplicated for reliability purposes - Google Patents

Improvements to data processing systems duplicated for reliability purposes

Info

Publication number
GB1241363A
GB1241363A GB5428469A GB5428469A GB1241363A GB 1241363 A GB1241363 A GB 1241363A GB 5428469 A GB5428469 A GB 5428469A GB 5428469 A GB5428469 A GB 5428469A GB 1241363 A GB1241363 A GB 1241363A
Authority
GB
United Kingdom
Prior art keywords
computer
signal
block
slig
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5428469A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of GB1241363A publication Critical patent/GB1241363A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1417—Boot up procedures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Software Systems (AREA)
  • Hardware Redundancy (AREA)
  • Computer And Data Communications (AREA)

Abstract

1,241,363. Digital computers. INTERNATIONAL STANDARD ELECTRIC CORP. 5 Nov., 1969 [8 Nov., 1968], No. 54284/69. Heading G4A. [Also in Division H4] A data processing system, for example, for controlling a telephone or telegraph exchange, comprises two identical digital computers which normally both operate simultaneously so as to be capable of operating the exchange, but only one of which actually controls the exchange so that if the controlling computer fails in any way the other computer takes over immediately. One computer ENS1 is shown in Fig. 1 with the other computer ENS2 (not shown) being leftwards thereof. The computer comprises a line block BL, a computing block BC, a ferrite core memory MF and a magnetic drum memory MT. In operation the block BL scans incoming lines REC, detects telegraph signals, processes them, and stores characters in the memory MF. The computer block BC takes the characters and forms them into messages which it stores in the memory MT together with operating instructions. When the message is to be retransmitted the block BC transfers it to memory MF from whence it is transmitted via block BL only if the gate pt is enabled by a signal SLIG. If the signal SLIG is not present no transmission is made from computer ENS but one is made from computer ENS2, and vice versa. An exchange memory ME ensures that both computers process at the same speed. Error detection in a computer.-A testing circuit CC receives periodic signals FAM from block BL and signals S11 from the block BC which indicate the respective units are still functioning. A signal FPR is sent when the computer programme is in error. If there are no errors, circuit CC sends a signal #FOT to a change over NAND gate PB which indicates whether computer ENS1 is on line or not. When ENS1 is on line, ENS2 is off line and produces a signal SLIG equivalent to #ADC, and the condition register RE provides signal LIG. Hence the NAND gate PB suppresses the signal #SLIG, and the computer ENS1 is on line as inverter IN provides signal SLIG to enable gate pt. If an error occurs, circuit CC sends signal FOT, the gate PB sends signal SLIG which is signal #ADC to computer ENS2, at the same time disabling gate pt. Hence the two computers ENS1 and ENS2 are immediately interchanged. The signal FOT goes to the block BC and causes a restart programme to commence (Fig. 2, not shown) which restores all the circuits of blocks BL and BC to zero, increases a failure counter by one and stops the computer if the counter has reached a certain level (the counter being periodically restored to zero). Otherwise it reloads the operating programme from drum TA and the computer is then ready to go on line again.
GB5428469A 1968-11-08 1969-11-05 Improvements to data processing systems duplicated for reliability purposes Expired GB1241363A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR173060 1968-11-08

Publications (1)

Publication Number Publication Date
GB1241363A true GB1241363A (en) 1971-08-04

Family

ID=8656650

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5428469A Expired GB1241363A (en) 1968-11-08 1969-11-05 Improvements to data processing systems duplicated for reliability purposes

Country Status (6)

Country Link
BE (1) BE741478A (en)
CH (1) CH520369A (en)
DE (1) DE1955721A1 (en)
ES (1) ES373353A1 (en)
FR (1) FR1591358A (en)
GB (1) GB1241363A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2000327A (en) * 1977-06-20 1979-01-04 Mitsubishi Electric Corp Elevator control apparatus
GB2146810A (en) * 1983-09-13 1985-04-24 Westinghouse Electric Corp Achieving redundancy in a distributed process control system
GB2280821A (en) * 1993-08-03 1995-02-08 Plessey Telecomm Telecommunications system employing mirrored processing
US5911038A (en) * 1993-08-03 1999-06-08 Gpt Limited High availability telecommunications system with a dual interface for mirrored asynchronous processing

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2486749B1 (en) * 1980-07-11 1987-10-30 Thomson Csf Mat Tel CONTROL UNIT AND TELECOMMUNICATIONS CENTER COMPRISING SUCH A CONTROL UNIT
FR2692379B1 (en) * 1991-10-04 1996-08-14 Aerospatiale Ste Nat Indle FAULT DETECTION AND PASSIVATION PROCESS IN A DATA PROCESSING SYSTEM, AND DATA PROCESSING SYSTEM ADAPTED TO ITS IMPLEMENTATION
US6151686A (en) * 1997-06-06 2000-11-21 Fmr Corp. Managing an information retrieval problem
US6631424B1 (en) 1997-09-10 2003-10-07 Fmr Corp. Distributing information using a computer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2000327A (en) * 1977-06-20 1979-01-04 Mitsubishi Electric Corp Elevator control apparatus
GB2000327B (en) * 1977-06-20 1982-04-07 Mitsubishi Electric Corp Elevator control apparatus
GB2146810A (en) * 1983-09-13 1985-04-24 Westinghouse Electric Corp Achieving redundancy in a distributed process control system
GB2280821A (en) * 1993-08-03 1995-02-08 Plessey Telecomm Telecommunications system employing mirrored processing
GB2280821B (en) * 1993-08-03 1998-01-28 Plessey Telecomm Telecommunications system
US5911038A (en) * 1993-08-03 1999-06-08 Gpt Limited High availability telecommunications system with a dual interface for mirrored asynchronous processing

Also Published As

Publication number Publication date
DE1955721A1 (en) 1970-09-03
ES373353A1 (en) 1972-01-16
BE741478A (en) 1970-05-11
CH520369A (en) 1972-03-15
FR1591358A (en) 1970-04-27

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