GB1193311A - Digital Instruments - Google Patents
Digital InstrumentsInfo
- Publication number
- GB1193311A GB1193311A GB40018/67A GB4001867A GB1193311A GB 1193311 A GB1193311 A GB 1193311A GB 40018/67 A GB40018/67 A GB 40018/67A GB 4001867 A GB4001867 A GB 4001867A GB 1193311 A GB1193311 A GB 1193311A
- Authority
- GB
- United Kingdom
- Prior art keywords
- stable device
- count
- counter
- displayed
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/02—Input circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/001—Analogue/digital/analogue conversion
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Meter Arrangements (AREA)
Abstract
1,193,311. Digital displays. STANDARD TELEPHONES & CABLES Ltd. 1 Sept., 1967, No. 40018/67. Heading G4H. To eliminate jitter in the last digit of a displayed count in which, whilst incoming pulses are being counted for a fixed time interval, the result of the preceding count is displayed, the incoming pulses are fed via a bi-stable device 7 (Figs. 3, 4) to the counter and, if at the end of the fixed interval, the bi-stable device is in its one state and the lowest digit a s of the count being displayed differs from the lowest digit a held in the counter a correction pulse is added in. In one embodiment (Fig. 3) at the end of the count, the output a of the least significant flipflop in the lowest decade of the counter is compared with the inverse a s of the least significant digit being displayed and if they are the same a " 1 " output from NAND gate 12 results in the output of AND gate 15 being " 0 " when a jitter correction pulse is applied so that, if the bi-stable device 7 is in its " 1 " state the zero output of NAND gate 8 is inverted and a pulse applied to the counter. In the second embodiment (Fig. 4) the gates precede the bi-stable device, the pulse fed to the bi-stable device if a and a s differ only affecting the count if the bi-stable device is in its " 1 " state.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB40018/67A GB1193311A (en) | 1967-09-01 | 1967-09-01 | Digital Instruments |
BE720274D BE720274A (en) | 1967-09-01 | 1968-09-02 | |
FR1599742D FR1599742A (en) | 1967-09-01 | 1968-09-02 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB40018/67A GB1193311A (en) | 1967-09-01 | 1967-09-01 | Digital Instruments |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1193311A true GB1193311A (en) | 1970-05-28 |
Family
ID=10412759
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB40018/67A Expired GB1193311A (en) | 1967-09-01 | 1967-09-01 | Digital Instruments |
Country Status (3)
Country | Link |
---|---|
BE (1) | BE720274A (en) |
FR (1) | FR1599742A (en) |
GB (1) | GB1193311A (en) |
-
1967
- 1967-09-01 GB GB40018/67A patent/GB1193311A/en not_active Expired
-
1968
- 1968-09-02 BE BE720274D patent/BE720274A/xx unknown
- 1968-09-02 FR FR1599742D patent/FR1599742A/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR1599742A (en) | 1970-07-20 |
BE720274A (en) | 1969-03-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PLNP | Patent lapsed through nonpayment of renewal fees |