GB1192144A - Semiconductor Device and Manufacturing Method thereof - Google Patents

Semiconductor Device and Manufacturing Method thereof

Info

Publication number
GB1192144A
GB1192144A GB4653268A GB4653268A GB1192144A GB 1192144 A GB1192144 A GB 1192144A GB 4653268 A GB4653268 A GB 4653268A GB 4653268 A GB4653268 A GB 4653268A GB 1192144 A GB1192144 A GB 1192144A
Authority
GB
United Kingdom
Prior art keywords
silicon
substrate
semi
silicon nitride
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4653268A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of GB1192144A publication Critical patent/GB1192144A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

1,192,144. Semi-conductor devices. HITACHI Ltd. 1 Oct., 1968 [2 Oct., 1967], No. 46532/68. Heading H1K. An insulating coating on the surface of a semi-conductor substrate comprises a silicon nitride film and an inorganic insulating layer containing silicon oxide and phosphorus oxide formed on the surface of the silicon nitride film. The silicon nitride film may be directly in contact with the semi-conductor substrate or may be separated therefrom by a layer, e.g. of silicon dioxide. Preferably a silicon substrate is exposed to an atmosphere containing nitrogen, ammonia and monosilane at an elevated temperature (875‹ C.) to form the silicon nitride film and then exposed to an atmosphere of oxygen and phosphorus oxychloride (POCl 3 ) at between 800‹ and 1200‹ C., preferably between 1000‹ and 1100‹ C., to form the silicon oxide-phosphorus oxide layer. The invention may be applied to a Metal- Insulator-Semi-conductor diode comprising an N-type silicon substrate and gold and aluminium electrodes, the aluminium electrode being separated from the substrate by the silicon nitride and silicon oxide-phosphorus oxide layers. A plurality of diodes is made on a silicon substrate which is subsequently divided to form the individual diodes. It is stated that the provision of the insulating layer of the invention improves the stability of the capacitance-voltage characteristics. Other applications described include a planar junction transistor having diffused emitter and base regions and an insulated-gate field-effect transistor. In both cases, selected portions of the insulating layers are removed by etching first with hydrofluoric acid and then with phosphoric acid to permit the introduction of the electrodes to the appropriate regions of the semi-conductor devices. A plurality of fieldeffect transistors may be formed in a single substrate and interconnected by metal layers applied over the surface of the insulating layers.
GB4653268A 1967-10-02 1968-10-01 Semiconductor Device and Manufacturing Method thereof Expired GB1192144A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6306367 1967-10-02

Publications (1)

Publication Number Publication Date
GB1192144A true GB1192144A (en) 1970-05-20

Family

ID=13218491

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4653268A Expired GB1192144A (en) 1967-10-02 1968-10-01 Semiconductor Device and Manufacturing Method thereof

Country Status (4)

Country Link
DE (1) DE1800348B2 (en)
FR (1) FR1586940A (en)
GB (1) GB1192144A (en)
NL (1) NL6814072A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0109766B1 (en) * 1982-10-22 1986-12-30 Fujitsu Limited Semiconductor device with a passivated junction

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5922381B2 (en) * 1975-12-03 1984-05-26 株式会社東芝 Handout Taisoshino Seizouhouhou

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0109766B1 (en) * 1982-10-22 1986-12-30 Fujitsu Limited Semiconductor device with a passivated junction

Also Published As

Publication number Publication date
DE1800348A1 (en) 1969-11-06
NL6814072A (en) 1969-04-08
DE1800348B2 (en) 1971-07-22
FR1586940A (en) 1970-03-06

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees