GB1189947A - Improvements in or relating to apparatus for Performing Multiplication - Google Patents

Abstract

1,189,947. Multiplication apparatus. INTERNATIONAL BUSINESS MACHINES CORP. 28 March, 1968 [15 April, 1967], No. 14870/68. Heading G4A. Multiplication is by accumulating selected pre-stored multiples of the multiplicand. For multiplication with binary-coded-decimal operands, multiples 1.0, 0.1, 1.1 of the multiplicand are stored in respective word locations of a store, the second multiple being obtained from the first by shift in an accumulator register and the third being obtained by adding the first and second. Two other word locations are provided for the multiplier and product respectively. Each byte (a pair of decimal digits) of the multiplier is passed in turn (low-order byte first) to a pair of registers (one per digit) where the two digits are decremented together, decrementing of each stopping when it reaches zero, until both are at zero. Each decrementing is preceded by addition of the 1.0, 0.1 or 1.1 multiple of the multiplicand into the accumulator register according as only the first (high-order), only the second or both the current values of the multiplier registers are non-zero respectively. When both these values are at zero, the contents of the accumulator register are stored in the product word location of the store, and also retained in the accumulator register where they are shifted one byte to the right thus losing the two lowest-order decimal digits. The next byte of the multiplier is now taken. Three address registers, capable of selecting word and byte, are associated with the store to address the product, multiplier and multiplicand-multiples respectively, the first two being decremented after each multiplier byte (to select the next byte position) and the values of two bits of the third being controlled by the registers into which the multiplier bytes are placed to select the appropriate multiplicand multiple. A second embodiment differs in also storing the 0.9 multiple (obtained by subtracting the 0.1 multiple from the 1.0), and adding or subtracting the multiples depending on whether the two multiplier digits are greater than five or not. In this case the registers storing the multiplier digits can be incremented as well as decremented. If the current value of neither multiplier digit register is zero or ten then (a) if both or neither are greater than five the 1.1 multiple is subtracted or added respectively whereas (b) if only the first (high-order) or the second is greater than five the 0À9 multiple is subtracted or added respectively. If only the first or the second multiplier digit register is not at zero or ten, then the 1.0 or 0.1 multiple is taken respectively, and in either case is subtracted or added according as the digit not equal to zero or ten is greater than five or not respectively. The 0.1 multiple could be generated by shifting when required rather than being stored. The multiples 2.0, 2.2, 0.2 could also be used formed using a doubler &c. The multiples could all be stored in separate addressable registers rather than a single store.