DE1549465A1 - Multiplier - Google Patents

Description

IIVMW ■ ■■■ *. »- ^, . _w

1549455

IBM Germany International Office MaiekinenGeeelUchafi mbH

Patent Department 7030 Boeblingen Sindelfinger Strasse 49

Boeblingen. February 20, 1967 km-h

Official ε file number: P 15 49 465. 2-53 Applicant's file number: Docket 866 077; GE 037 Multiplier . . ·: '

The invention relates to a multiplication device with means for forming and accumulating multiplicand multiples. * lv * _v

It is with multipliers that operate on the principle of continued Addition of the multiplicand is known to work in addition to the single multiplicand as well as the double multiplicand for the accumulative formation of the product to use (R. K. Richarde: "Arithmetic Operations in Digital Computers", New York, 1955, pages 252-255). For this purpose, double the value of the multiplicand is always generated, and depending on the value to be processed Multiplier number determines how often the single and / or double multiplicand value is to be added. After that there is a post shift between the partial product formed and the multiplicand field and with the processing of the next multiplier make * treat. A multiplication of the multiplicand by the multiplier number is thus, for example, instead of a sixfold addition of the one

108808/1587

New documents

times the multiplicand by adding three times the double multiplicand executed. There are also known multipliers which also have single and double multiplicand values Use multiplicand multiples in the same way to get the

Reduce the number of addition iterations per multiplier digit.

It is also known for such devices (pages 260 to 261 of the mentioned book) to shorten the multiplication operations further by adding the multiplicand or its multiple to the already The partial product formed is added or subtracted from this, depending on whether the multiplier number to be processed is smaller than six or greater than five. If subtractions are carried out, a one must be added to the next higher multiplier number. This is a tenfold addition of the multiplicand with respect to the multiplier to be processed by performing subtractions achieved.

There are also known multipliers in which each only one multiplier digit with several multiplier digits at the same time is multiplied in the manner explained above (pages up to 267 of the book mentioned). The partial products formed in the process become summarized in an accumulator plant. A full multiplication is always executed * when all «multiplicand digits have been processed one after the other.

109808/1587

Docket GC 866 077

Furthermore, a lot of thought has been given to one To build a multiplication device «which works in parallel to the extent that the digits of two multi-digit operands with the help of a number of one-time tables are multiplied at the same time (z. B. A. P. Speiser: "Digitale Rechenanlagen", Berlin 1961, pages 199, 200). The effort however, the number of switching means in such a device is far above the level that is acceptable in practice. "

The object of the present invention is to provide a multiplication device, compared to the known, with iterative addition or with optional addition and subtraction working devices without one Significant additional work on components allows a higher working speed. According to the invention this is achieved in that the multiplier digits in pairs of a control register circuit are supplied, which depends on whether the higher-digit which low-digit or none of the two digits is zero, the selection below 0.1, 1 or 1, 1 times the multiplicand controls which is then added to a partial product as often as the number deviating from zero or the smaller one indicates.

A major advantage of such an arrangement is that that the number of additions or optional additions and subtractions and also the number of position shifts between the partial product already formed and the multiplicand field through the pa-

109808/1587

Docket GE 866 077 BAD ORIGINAL

Parallel processing of two multiplier digits each time greatly reduced will.

Further advantageous refinements of the invention can be found in the claims to see. The following are two embodiments of the invention explained on the basis of drawings. Show it:

Fig. 1: a block diagram of a designed according to the invention

Multiplication device, which with repeated addition of the multiplicands or certain multiples thereof is working,

Figure 2 is a detailed block diagram of a clock for use in the device according to FIG. 1,

3: a pulse diagram to explain the operation of the

Arrangements according to FIGS. 1 and 2,

Fig. 4: the association of Figs. 4A and 4B,

Fig. 4A and 4B: a block diagram of a further advantageous embodiment ' form of the multiplication device according to the invention, the works with optional repeated addition and subtraction of the multiplicand or certain multiples of the same,

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Docket GE 866 077

Figure 5 is a detailed block diagram of a clock for use in the device according to FIGS. 4A and 4B and

6: a pulse diagram to explain the mode of operation of the arrangements according to FIGS. 4A, 4B and 5.

The embodiment of the multiplication device according to the invention shown in FIG. 1 has an adder 1, an accumulator register 2, a memory 3 and various addressing this memory « serving registers 4 to 6. The memory 3 can be, for example, the main memory of the data processing unit in which the multiplication device Is used. Its output is connected to one operand input of the adder via a gate circuit 7. The output of the accumulator register is on the one hand via a Gate circuit 8 / n with the other operand input of adder 1 and on the other hand connected to the input of the memory 3 via a gate circuit 9. The adder 1 is in the example shown as binary decimal Parallel adder designed, which has so many digits, how they have the factors to be multiplied. Every decimal place consists of four binary digits. In Fig. 1 each as simple lines The input lines of the adder shown here therefore consist of a number corresponding to four times the number of operand digits. individual cores, each of which has a separate · gate in the gate circuits 7 and 8 is assigned. The accumulator register 2, since,

is designed as a shift register, has "for receiving the

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Docket OE 866 077. BATH ORIGINAL

Result digits from the adder 1 suitable number of control levels. The transmission line from the exit, shown as a single line de · Register 2 at the input of the memory therefore includes a dem A number of wires corresponding to multiples of the number of register positions, each of which is assigned a separate gate in the gate circuit 9. The content of register 2 is increased by a clock pulse t3B by two decimal places » d. H. thus shifted to the right by two binary tetrads.

The output of the memory 3 is also connected via a gate circuit 11 to two counting registers 12, 13, each of which is set up to receive a multiplier gate. Since register 12, which is referred to as a register, is used to hold the higher-digit number and register 13, which is referred to as b-register, is used to hold the lower-digit citation of the memory 3 via the gate circuit 11 at the same time extracted multiplier pairs ·.

The memory 3 has five memory fields in addition to other memory fields on, de are required to operate the multiplier shown. Ea is a multiplier field Mr, a product field Pt and three Mulüplikand fields Md-I, Md-Π and Md-ΙΠ. According to the Invention, two multiplier digits a, b are processed at the same time. For this purpose, at the beginning of each multiplication operation in the multiplicand field Md-I the! «Times multiplicand 1.0Md, in the

109808/1587

BAD ORIGINAL Docket CC 866 Ot?

Multiplicand field Md-II the O, Hache of the multiplicand and into that Multiplicand field Md-III the 1, part of the multiplicand entered. Depending on the value of the two digits a, b of the one to be processed One of these values is selected in each case by multipliers and pairs of digits. If both digits a and b are not equal to zero, · ο takes place a selection of the fields Md-III. If the lower digit (b) of the two digits is zero and the higher digit (a) is not equal to zero, the field Md-I of the simple multiplicand selected. In the opposite case, if a e 0 and b / 0,, the field Md-II of the 0 «waking multiplicand becomes selected. Finally, at a / 0 and b / 0, the field Md-III des 1, guards multiplicand selected. This selection is made with the help of two separately controllable stages 22, 23 of the register 6, the Serves via the gate circuit 21 for addressing the multiplicand fields.

The multiplicand fields Md-I ₁ Md-II and Md-IH are arranged in the memory in such a way that their addresses differ only in two binary digits, while the other address positions are common to all three fields. These two binary digits are assigned the register stages 22, 23, which correspond completely to the other stages of the register 6, but independently of these via separate input lines 24,. 25. are adjustable. An address bus 26 is used to set all the other stages of the register 6. The register stages 22, 23 preferably correspond to the two lowest binary parts of the address

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Docket GE 866 077 BAD ORIGINAL

1 O Md-I O 1 Md-II 1 1 Md .ΠΙ

of a memory word so that the three multiplicand fields in the Memory 3 are on adjacent memory words. If the content of the register level 22 is V and the content of the register level 23 is designated by W, the following assignment results:

VW Multiplicand field Multiplicand multiple

1.0
0.1
1.1

The part 27 of the register 6 located on the right of the stages 22, 23 is used to receive those address locations which, in a manner known per se, designate the memory locations or bytes of a memory word. You can enter the address of the first digit of an operand field, e.g. D. Specify the multiplicand field Md-I if this position does not match the first position of the relevant memory word.

The setting of the register levels 22, 23 takes place under the control of the registers 12, 13. Each; this register consists of four flip-flop stages FF, which are linked in a manner known per se to form a counting circuit. These counting circuits are gradually switched to zero by means of Taklimpulae tlB, starting from the multiple digits entered into registers 12, 13 via line 14. The zero-Schaltzußtänden the Flipilops FF in the register \ £ corresponding outputs are connected to <iinnr And circuit 30th IJi · - corresponding outputs

10 9 8 0 0/1 f. "?

BATH ORIGINAL

The registers 13 are led to an AND circuit 31. The outputs of the two AND circuits 30, 31 are connected via an inverter circuit 32, 33 and an OR circuit 34, 35 to the inputs of the register stages 22, 23. Since the outputs of the AND circuits 30 and 31 are only signal-carrying when the stages of the registers 12 and 13 are in the zero state, the signal appearing at the output of the inverter stages 32 and 31 is an indication of this that there is a value other than zero in register 12 or. These display signals are denoted by a 'and b ¹ , where a ^{1 is} the state "multiplicand digit a in the register

12 is not equal to zero "and b 'has the status" multiplicand digit b in the register

13 show non-zero "on the lines 24, 25, these signals are used to directly adjust the register stages 22, 23 de · register 6 by, in a known per se,. Example, in a ^1" 1, the register stage 22 to one, and is set ^{to zero at a 1} a 0. The signals a \ b ¹ also reach gate circuits 38, 39 via which the clock signals tlB al «counting pulses are fed to the registers 12, 13. After the content of these registers has become zero, prevent the gate circuits 38, 39 a further supply of the counting pulses.

The registers 4 and 5 are used to address the other fields shown in FIG. 1 in memory 3, namely the product field Pt and the multiplier field Mr. During the multiplication, these addresses are sent by means of gate circuits 42, 43 under the action of suitable clock pulses t2A and tOA sum memory 3. Each of the registers 4, 5 is assigned an address modification circuit 44, 4 5, via the Docket GE 866 077 M at suitable times.

- ίο-

of the multiplication process by clock pulses t3B in the registers are reduced by one in each case.

A clock generator 50, which is shown in FIG. 2 and which generates a pulse program as shown in FIG. 3, is used to generate the various clock pulses required for operating the device according to FIG. 1. The clock has a pulse generator 51 which alternately generates tA and tB pulses as long as a control signal is present on a line 52. Another component of the clock 50 is a counter 53, which consists of two flip-flops and which is known per se is set up so that it can count from zero to three »Signals t0 to t3 are generated by the output lines 54 to 57 and AND circuits 58 to 61 assigned to the switching states of the two flip-flops. The signal tO passes together with the clock signals tA from the generator 51 to an AND circuit 62, which supplies a clock signal tOA at its output, and together with the clock signals tB to an AND circuit 63 which has the clock signal tOB at its output supplies. AND circuits 64 and 65 are used to generate corresponding clock signals tlA, tlB. The line 37 carries a signal a '+ b' which is generated by the inverter circuits 32 and 33 ^{from the signals a ·, b 1} with the aid of an OR circuit 36 (FIG. 1). The AND circuit 64 therefore always only supplies clock signals t1A when the content of at least one of the registers 12 and 13 is not equal to zero. The same condition applies to the clock signals tIB from the AND circuit 65, which at a first input the

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Docket GE 864 077 'BAD ORIG.NAL

Clock signals tB, the signal ti at a second input and the signal a ¹ + b ¹ at a third input. And circuits 66 and 67 are used to generate clock signals ÜZA and t2B. The AND circuit 66 receives input signals from the ti line and from the tA output of the clock generator 51 and, via an inverter circuit 68, the signal a ¹ + b ¹ . The signal t2A is thus always generated only when the content of both registers 12 and 13 (FIG. 1) is zero at count 01 in 53. The AND circuit 67 supplies an output signal tZB when the signal lines t2 and tA are jointly carrying signals. An AND circuit 69, which is connected to the signal lines tB and t3, is used to generate a further clock signal t3B. The signals tOB, t2A, t2B and t3B from the AND circuits 63, 66, 67 and 69 cause the counter 53 to advance to the next switching state via the OR circuit 70 when they occur. When the last clock signal t3B occurs, the counter 53 is reset from count 3 to count 0, with which a new clock cycle begins.

Of the decimal Multipükationsbeispieles 3 57 46 2.0 9To χ is hereinafter explained s 16 53 49 8.0 The operation of the arrangement of FIG. 1 on hand. The operation begins with the fact that in a preparatory phase the multiplier 46 2.0 in the field Mr of the memory 3 and the multiplicand 03 57 9.0 with its corresponding multiples in the fields Md-I, Md-II and Md-III of the memory 3 can be adjusted. Entering the multiplier and the multiplicand in the fields Mi * and Md-I

1088087158?

BATH ORIGINAL

happens in a known and therefore not to be explained in detail. All that needs to be mentioned is that while the multiplicand address is being supplied via the collective address line 26, a pulse P1 via the gate circuit 34 brings the register stage 22 to the one state, while the stage 23 remains in the zero state. The multiplicand is then taken from the memory 3 and transferred to the accumulator register 2 while maintaining the address set in the register 6 and transferred to the memory by a pulse P2. This takes place under the effect of clock pulses in P3. A clock pulse P4 shifts the content of register 2 by one decimal place to the right. Then the register stage 23 is set to one by a clock pulse PS via the OR circuit 35, while the register stage 22 remains in the zero state due to the absence of a pulse P1. A clock pulse P6 transfers the content of register 2, which represents the 0.1 «cache of the multiplicand, back to memory 3, namely to the now addressed field Md-II. Then, under the effect of a new sequence of clock pulses P1, P2, P3, P4, P2 _f P3, the contents of both fields Md-I and Md-H are added once. The result corresponding to 1.1 times the multiplicand is transferred back from register 2 to the memory with the aid of a P6 pulse, after register stages 22 and 23 have been set to one by the joint occurrence of one pulse P1 and P5, see above since the address of the field Md-ΙΠ has been transferred to the memory 3 via the gate 21 by a pulse P2. The clock pulses P1 to P6 are generated in a known manner by a special clock generator or by a corresponding microprogram input.

? ■

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SAD ORfGiNAL Docket GE 866 077

15Λ9465

direction generated. This also takes place in a manner not shown by these means a reset of the counter 53 to zero.

The preparation phase is now over. Like the table below
I shows, the multiplier value 46 £ 0 is thus in the memory field
Mr ₁ the simple multiplicand value 03 57 9.0 in the memory field Md-I, the 0.1-fold multiplicand value 35 7.9 in the memory field Md-II and the I ^ 1-fold multiplicand value 03 93 6.9 in the memory field Md- III.

Content of Mr:
Content of Md-I:
Content of Md-II:
Content of Md-III:

TABLE I

46 2.0 03 57 9.0

35 7.9 03 93 6.9

(1.0 χ Md) (0.1 χ Md) (1.1 χ Md)

Execution phase
χ 1, 0 Md

χ 1.1 billion

χ 0.1 Md *

03 57 9, 0 03 57 9.0 07 15 8.0 00 07 1 5 (8.0)

03 93 69 35 79

■ 35 79 16 53 49

V = 1 W = 0

Save partial product

Partial product in Acc-Reg. move two steep to the right

4 · »V ■ 1 6 ^ Ws 1

a s 0 * V s 0 b β 2 ·> W a-. I.

Save partial product to Pt address -1

product

Docket GE 866 077

16 53 49 8.0

109808/1587

BATH ORIGINAL

The numerical "course of the multiplication operation can be seen on the basis of this Blackboard to be traced. The start signal is given by a control signal on line 52, which activates the clock pulse generator 51 given for the beginning of the actual multiplication operation. Of the Clock pulse generator 50 reacts to this by generating a clock pulse tOA (FIG. 3) through which the address of the lowest byte of the multiplier field β Mr is transferred to the memory 3. The following Clock pulse tOB carries the two digits, the addressed and contains 3 bytes read out from the memory, via the gate circuit to registers 12, 13, whereby the higher digit (a »2} in the a register 12 and the low-digit number (b s 0) are set in b register 13 will. Since the "" register 12 now contains a value other than zero, the AND circuit 30 does not provide an output signal, so that an output signal a * is generated by the inverter circuit 32. in the In contrast, since the content of the b register 13 is zero, the AND circuit 31 carries signals, so that the inverter circuit 33 does not Output signal b 'generated via the OR circuits 34 and 35 are therefore register levels 22, 23 of register 6 according to V » and WsO discontinued. Together with the content of the other register positions the register 6 therefore contains the address of the multiplicand field Md-I. The a 'signal arrives via the gate circuit 36 and the line 37 to the clock generator 50 and there conditions the AND circuit 64, so that when the next tA pulse occurs, a clock signal tlA is output, gang of this AND circuit appears. This signal opens the gate circuit

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BAD ORIGINAL Docket GE 866 077

Zl in Fig. 1, whereby the address from register 6 to memory 3 is transmitted. The signal from line 37 also opens the AND circuit 65 of the clock 50 (Fig. 2), go that the following tB pulse generates a clock signal UB via this AND circuit »that the gate circuit 7 (Fig. 1) opens «whereby the content of the MultipU-kandenfeldes Md-I via the adder 1 sum accumulator register 2 is transmitted. Due to the clock pulse tlB, the a-Regi-, ster 12 has been switched back by the value 1 towards zero. It contains hence the value 1. Because for this reason the AND circuit 30 not conducting and line 3? remains signal-carrying, it just becomes described process repeated, d. That is, via the AND circuit 64 of the clock generator 50, a ti A signal and the AND circuit 65 generates a tlB signal which cause the contents of the Md-I field is again removed from the memory 3 and transmitted to the adder 1 via the gate circuit 7. There this value becomes the content of the register »2, the gate circuit opened by the clock pulse tlB 8 to the second operand input of the adder 1 added. With the new clock pulse tiB, the Contents of the a-register 12 again reduced by one, so that this register now contains the value Hull. As a result, the AND circuit 30 becomes conductive, so that the signal a * at the output of the inverter circuit 32 disappears and the OR circuit 36 also becomes non-conductive. There line 3? now there is no signal, the AND circuits remain 64 and 65 locked in the clock 50. On the other hand, the AND circuit

. 109808 / 1S87 bathroom

Docket GE 866 07?

66 prepared for a pulse generation by an output signal from the inverter circuit 68. With the next tA pulse, a clock signal t2A occurs at the output of this Und circuit, which opens the gate circuit 42 (FIG. 1). This transfers the address of the product field · Pt sum memory 3. The same clock signal t2A advances the counter 53 of the clock 50 by one step via the OR circuit 70 (FIG. 2), as a result of which it now generates a signal t2 via the AND circuit 60. This signal conditions the AND circuit 67, which emits a clock signal t2B at the next tB time. This signal opens the gate circuit 9 (FIG. 1) for transferring the contents of the register 2 into the addressed memory field Pt. Although the partial product 715 $ O formed up to now has been stored in the field Pt, the same value also remains in register 2. The clock pulse generator 50 next supplies a clock signal t3B in the manner described. Contents of the · accumulator register · 2 shifted by one byte, ie two decimal places to the right. As a result, the two lowest digits of the contents of register 2 are lost. The clock signal t3B also makes the address modification circuits 44 and 45 effective, via which the contents of the registers 4 and 5 are reduced by one in each case. The addresses stored in these registers are

thereby on the second byte (from the right) of the memory fields Mr and Pt has been switched. Since the clock signal t3B but the OR circuit 70 keeps the counting circuit 53 at zero, a '

Docket GE 866 077

109808/1587

BATH ORIGINAL

new cycle of the clock 50 initiated. This new cycle begins again with the generation of clock signals tOA and tOB, which cause the now addressed second multiplier byte to be transmitted to registers 12 and 13. This byte contains the third and fourth decimal places of the multiplier, i.e. its second highest and highest digit with the values 6 and 4. The multiplication of the multiplicand with these two multiplier digits is the same as the multiplication with the first two multiplier digits and can easily be based on the above Table I to be traced. As can be seen from table I, the 1. I times multiplicand 03 93 69 from field Md-ΙΠ is added four times during the second clock cycle. Since both the content of register 12 and the content of register 13 are not equal to zero at time tlA of this cycle, signals a "and b" occur at the outputs of inverters 32 and 33, which cause stages 22 and 23 must be set according to V »1 and WsI for addressing the field Md-ΠΙ. After four times the addition of the 1. I times the multiplicand 03 93 69 takes place in the same clock cycle, the 0.! Times the multiplicand 35 79 is added twice .The clock signal tlB has been reduced to zero. Since at this time the content of the b register 13, which has been reduced to the same extent, is still two, the register stages 22 and 23 are set according to V »0 and Wal to *

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Docket GE 866 077 'BATH

- ie -

Addressing of the field Md-Π in the memory 3. After the content of the register 13 has also been reduced to zero during the next two tlA- ti B cycles, the absence of signals a ¹ and b ¹ causes the clock 50 to generate the Clock signals t2A, t2B and t3B are advanced in the manner described. These clock properties cause the partial product accumulated in register 2 to be stored in the product field Pt in the memory 3. digits overwritten, so that the content of the product field Pt at the end of the "wide clock cycle" the product 16 53 4 $ BfifmUiS.lt, from which the two lowest positions (Bj 0) in the first clock cycle and the other positions in the "wide clock cycle were generated . The multiplication operation is thus finished.

Another advantageous embodiment of the multiplication device according to the invention can be seen from Figures 4A and 4B. The arrangement shown there works with the optional addition and subtraction of the Multiplicands or their multiples, depending on whether the two multiplier digits to be processed in parallel are less than six or greater than five.

Connection with In Figs. 4A and 4B are those parts which the already inTFig.

parts described correspond, with the same reference numerals, however additionally provided with a 'symbol. Of these parts only show the adder 1 * (Fig. IB) and the registers, 12 * and 13 * (Fig. 2A) additional functions. The adder 1 'is in contrast to the

109808/1687 bath

Docket GE 866 077

.ι, - Ί549465

Adding unit I of FIG. 1 optionally via control lines 71 «72 the execution of additions or subtractions adjustable. To the* correspondingly, the a-register 12 'and the b-register 13' are In for well-known catfish designed as a number register »which optionally through Control lines 73 «74 bsw. 75, 76 by +1 or * l, so in the sense an increase or reduction of the respective register contents a, be switched on.

The main difference in the mode of operation of the device according to FIGS. 2A and 2B compared to the device according to FIG. 1 is that "0.9 times the multiplicand is used" if the digits a and b "in a multiplier byte to be processed not equal to zero and one of them is greater than five. In this case, instead of adding the 1.1 times the multiplicand, the multiplication is carried out by adding or subtracting the 0.9 times multiplicand, the number of these subtractions being determined by the tens complement of the relevant multiplier digits. There are accordingly four · MuI-UpUkand fields provided in the memory 3 *, which have the designations Md-I ¹ , Md-U ¹ , Md-in ¹ and Md-IV and those in the stages 22 · and 23 * of the register 6 ¹ storable binary digits V and W can be distinguished. The following relationship exists between the memory fields mentioned and the binary address numbers V 'and W ^1:

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Docket GE 866 077 BAD ORIGINAL

Md-I ' O O Md-II ' 1 1 Md-III 1 O Md-IV

V ¹ W Multiplicand storage field multiplicand multiples β

1.0 0.1

0.9

The address numbers V and W are determined as a function of the two digits a and b of a multiplier byte introduced into the counting registers 12 ', 13'. As in the example according to FIG. 1, the flip-flops β of these registers are scanned for a zero content via AND circuits 30 * and 31 '(FIG. 4), and the output signal of these AND circuits is via inverter circuits 32', 33 * converted into signals a ¹ and b ¹ . The appearance of these signals a ¹ and b 'thus indicates that the digits a and b contained in the registers 12' and 13 * are not equal to zero. The same output signals are generated when

Output signals from AND circuits 78, 79 in the associated register

decimal
12 · or 13 * show the value 10, which can result from counting up during the execution of subtraction iterations. For this purpose, the AND circuits 78, 79 are connected to the one outputs of the register levels of the binary digits 2 and 8 and xdt to the zero outputs of the remaining registers of the binary digits 1 and 4 in the associated registers 12 * and 13 *.

In addition, display signals et and β are derived from the register content. The signal oc indicates that the content of the a-register 12 ', i.e. the

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Docket GE 866 077

Multiplier digit a, greater than five iat. The signal β means that the content of the b register 13 / alio the multiplexer b, is greater than five. The * and β signals are generated with the aid of an AND circuit 80 and an OR circuit 82 for the register 12 * and with the aid of an AND circuit 81 and an OR circuit 83 for the register 13 '. For example, the AND circuit 80 is connected to the one outputs of the register stages of the register 12 * assigned to the binary digits 2 and 4. The output of this AND circuit leads to an input of the OR circuit 82, which also scans the one output of the register stage of the binary value 8 via a second input. The OR circuit 82 therefore supplies an output signal <* if the a-register 12 'contains the digits tt _f 7, 8 or 9) This signal arrives when a clock signal t2B occurs via an AND circuit 84' to a Flip-flop 86 and is temporarily stored in it * The one output of flip-flop 86 is assigned to signal oo and its zero output is assigned to signal o *. In the same way, the AND circuit 81 and the OR circuit 83, depending on the content of the b-register 13 ', the signal β. which is not cached, but used directly. Intermediate storage of the Of signal is only necessary to control the addition of one to the next higher multiplier number, i.e. the b-digit of the next multiplier byte, if the a-digit of the byte currently being processed is greater than five and therefore controls the execution of subtraction iterations. . ,

109808/1587

BAD ORIGINAL Docket GE 866 077

• cc -

^{Signals a 1} , b ¹ , α derived from the contents of registers 12 and 13 'in the manner described. and j & result according to the following table Π the associated address numbers V and W * for the selection of the required multiplicand multiple as well as the control signals ADD, SUB on lines 71, 72 for the respective control of the adder »1 * for the execution of additions or Subtractions.

TABLE II

away' 0 β V ¹ W * 1 Multiplicands
multiple Multiplicands
Storage field Red
tax « 1 1 1 0 1 1 1.1 Md-ni ¹ ADD 1 1 0 1 1 0 1.1 Md-III ' SUB 1 1 .1 1 1 0 0.9 Md-IV ADD 1 1 0 0 1 1 0.9 Md-IV SUB 10 1 0 0 1 1.0 Md-I ' ADD I 0 0 0 0 1.0 Md-I ¹ SUB 0 1 0 0 0 0 0.1 ' Md-n ADD 0 1 1 0 0.1 Md-Π ' SUB

Using table Π, the following logical relationships can be derived for the digits V and W:
V ¹ ■ J

W · «(e-j8 + ST fi) ä« b «>a'b · V.

The following logical relationships can also be used for the arithmetic unit Derive control signals ADD and SUB on lines 71, 72:

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BATH ORIGINAL

Docket GE 866 077

I v # "t V ^ τ

ADD. ■ a ¹ «* +;

SUB «a W + an» «^ ΐ ADD '. ■■ <■ 7 · ~ ·. ■

A logic circuit 85 (FIG. 4B) is constructed in accordance with the principles of circuit algebra according to these relationships. In addition to the signals a ', b \ o * and β, it receives their complements a', b ¹ , o <and β on separate lines and supplies the output signals V and W as well as ADD and SUB. The signals V and W ¹ are passed to the input of the stages 22 · and 23 'of the register 6 *, and the signals ADD and SUB pass via the lines 71, 72 as operational control signals to the adder-subtracter £' «

To generate the for the operation of the shown in Figs. 4A and 4B Multiplication device necessary clock signals is used a clock generator 90, the structure of Fig. 5 can be seen and the one Pulse program according to FIG. 6 erseugt. The clock generator 90 is constructed similarly to the clock generator 50 of FIG. It is different from this one only by defining five clock signal pages ti to t5 and therefore a counter 53 * is used, which consists of three binary levels. Each of the signals ti to t5 is routed to two AND circuits, (e.g. tO to the AND circuits 91 * 92), which are used as the second input signal receive a clock pulse tA or tB and generate a clock signal tOA to t4A or tOB to t5B. To control the iterative addition and sub traction cycles, the clock signals t3A and t3B are used by the

109808/1587

BAD ORIGINAL Docket GE 866 077

. 84. ■ 1B49A65

AND circuits 94, 95 are generated. These AND circuits are supplied via a line 37 'da * signal a ¹ + b'. The function of the AND circuits 94 * 95 and a further AND circuit 96 generating the clock signal t4A corresponds to the function of the AND circuits 64, 65 and 66 in FIG. 2. The AND circuits 94 and 95 are pulsed by the Taktim tA and tB made alternately signal-carrying as long as the signal a '+ b' is present on line 37 '. If this signal subsides, then the AND circuit 96 is conditioned via the inverter circuit 68 'and thus the t3A-t3B cycles are aborted and the clocking continues. The last clock signal t5B of a clock generator circulating β serves, among other things, to reset the counter 53 * to the zero state, whereby a new clock generator cycle is prepared by generating the signal t0. ^;

In the following, using the multiplication example 3 57 9.0 χ 46 2.0 = 16 53 49 & 0 below shows the mode of operation of the device according to FIGS. 4A and 4B Referring to Table III below.

109808/1587 ^ß AD original

Docket GE 866 077

TABLE III

Preparatory phase
Content of Mr:
Content of Md-I ¹ :
Content of Md-U ':
Content of Md-IIT:
Content of Md-IV:

46 2.0 03 57 9 * 0

35 7.9 03 93 6.9 03 22 1.1 (1.0 χ Md)
(0.1 χ Md)
(1.1 χ Md)
(0.9 x Md)

Export out of phase

2 χ 1.0 Md

4 χ 0.9 Md

1 χ 1.0 Md

^r O3 57 9.0 03 57 9.0 07 15 8.0;. a * 1. »» O) VaO, b • w 0. P » OJ W ¹ » 1

Save partial product

00 07 1 5 (8.0) Part Prod. in acc. reg. two digits move to the right

16 53 49

b - 6, V »1 A- l) da.

* .l. a «4 ^ 5 ί 1.1 I a = 5. a '= 1 <*« Oj

aal, a »* 1 <* a 0) V» ba 10, b ¹ a 0 β a OJ W »Save partial product to Pt address 1

Product:

16 53 49

Analogous to the processes described in connection with FIG. 1, the multiplier 46 2.0 is entered in the field Mr and the multiplicand 03 57 9 * 0 in the field Md-I * of the memory 3 in a preparation phase. In addition, 0.1 times the multiplicand (35 7.9) is stored in the memory

1OiSSt / 1SB7

BAD ORIGiNAU

Docket GE 866 077

15A9A65 U

field Md-Π ¹ »da · 1.1-fold« d © a multiplicand (03 93 6.9) in the storage field Md-in ¹ and the 0.9-fold de · multiplicand (03 22 1.1 ) stored in the memory field Md-IV. This takes place in the manner described in connection with FIG. 1 using suitable clock pulses P. Fflr the supply of suitable clock pulses P su to the register stages 22 * and 23 * are OR circuits 34 'and 35 * in analogy to the arrangement according to FIG i provided. The 0.9 times the multiplicand is obtained by subtracting the 0.1 times multiplicand from the 1 times multiplicand

109808/1587 ■ "« orb-n «.

Docket GE Ub QU

It

obtain.

When a control signal is applied to line 52 (FIG. 5), the actual multiplication operation begins in that clock generator 90 begins its rate cycle. Due to the clock signal tOA, the multiplier address is transferred from the register 5 via the gate circuit 43 * sum memory 3 ', and the following tOB clock signal brings the first multiplier byte via the gate circuit II ¹ eu to the registers 12', 13 ' . The next clock signal ti A scans the one signal output of the flip-flop 85 via an AND circuit 100 for the presence of an o * signal. Wire such a signal from a previous clock cycle is present, o the content of the deajb register 13 * would be increased by one via an OR circuit 101 and the control line 75. In the present case, however, the flip-flop 85 is at zero ·And. in which it only emits a «* signal. A clock signal tIB then occurs at the reset gear of the flip-flop 85, bringing it into the zero switching state, provided it is not already in this state, as in the present case. In the same way, the next clock signal t2A via the AND circuit 102 and the OR circuit 103 makes the signal line 73 effective by increasing the contents of the a register 12 *, if After entering the new multiplier byteft at the output of the OR circuit 83, a P signal arrives via line 104 at a wide input of the AND circuit 102. In the present case, the content of the b register is 13 *

109808/1587

BAD ORIGINAL Docket GE 866 077

- ar -

ig

Zero, so that line 104 carries no signal, and the AND circuit 102 remains blocked. The subsequent clock signal t2B is conditioned the AND circuit 84. However, since the OR circuit 82 has no output signal returns (in the »register 12 'there is the value 2, i.e. smaller than 5), the AND circuit 84 remains closed and the flip-flop 85 (cc) in the zero state.

In the meantime, based on the digits a β 2 and b »0 in the registers 12 * and 13 *, the logic circuit 85 has the signal combination ι ¹ « 1, ä · · 0, V t 0, b · ■ 1, «c β fl, "* * 1, P s 0, ji s 1. The logic circuit 85 forms the address digits V * -0 and W« I from this signal combination, which are fed to the stages 22 'and 23' of the register 6 * This address is switched through to the memory 3 * by the following clock pulse t3A via the gate circuit 21 '. The next clock pulse t3B transmits the content of the addressed field Md-I * via the gate circuit 7 'and the adder-subtracter 1' to the accumulator register 2 *. At the same time, the t3B clock signal conditions the AND circuits 105, 106, 107 and 108. The second input of the AND circuit 105 receives the signal «&, the second Input of the AND circuit 106 the signal oC »the second input of the AND circuit the signal ρ and the second one output of the AND circuit 108, the signal β is supplied. The AND circuits 106, 108 each have a third input to which the signals a 'and b' are applied. Since ot and β are each zero, only the AND circuits are activated by the clock signal t3B

109808/1587

BAD ORIGINAL Docket GE 866 077

105 and 107 carry signals. The outputs of these AND circuits are connected to control lines 74 and 76 which, when energized, cause the contents of registers 12 * and 13 * to be reduced by one will. However, this operation is only effective in register 12 *, since the Register 13 'already contains the value zero, and therefore the AND circuit 108 is blocked due to the absence of the signal · b *. The register 12 'contains thus now the value one.

Due to the number of bytes since the first multiplier byte was entered in the register 12 'and 13' present conditions a '■ 1, the control line 37' leads a signal which via the inverter circuit 68 'and 96 (Fig. 5) a handover of the counter 53 'prevented, so that the clock 90 a new one t3A-t3B clock proper cycle generated. The new clock signal t3A the field Md-I * in memory 3 is addressed again and to the following t3B time, the content of this field is added to the content of the accumulator register 2 '. This register now contains the partial product 07 15 8.0 (see panel III). Since at the same t3B time the content of the a-register β 12 ' has been reduced by one again, this register now contains the Value zero, so that the signal on line 37 'disappears, so that the AND circuits 94 and 95 (FIG. 5) blocked and the AND circuit 96 conditioned will. When the next tA clock pulse β occurs, the clock generator switches 90 to the next switching state t4.

The then generated clock pulse t4A transmits the in register 4 * contained product field address by opening the gate circuit 42 · sum

109808/1687

Docket OE 866 077 . , BATH ORIGINAL

JO

Memory 3 ¹ . The following clock pulse T4b transmits "ueen contents of the accumulator register and s 2 'to the addressed field product Pt. ¹ By the last clock signal t5B of the first clock cycle, the content of the accumulator register 2 'is shifted by one byte to the right in the manner described in connection with FIG. The same clock pulse also causes the addresses contained in registers 4 'and 5 ^{1 to be} reduced by the value one. The clock signal t5B also resets the counter 53 '(FIG. 5) to the zero state, as a result of which the clock generator 90 is prepared for the beginning of a «new cycle.

The next multiplier byte, which comprises the multiplier digits 4 and 6, is entered into the registers 12 'and 13' by the clock signals tOA and tOB. After this operation, the logic circuits connected to the individual stages of these registers generate the signal conditions Κ * ;. » 1. * 7 ~ * 0. * «0, ~ K · 1, Β» - 1. b ⁷ "» 0, ßm 1, ~~ f a O. The condition ß » 1 causes, at cycle time t2A, that the AND circuit 102 becomes conductive and sends a pulse to control line 73 via OR circuit 103. As a result, the content of a register 12 'is increased by one, i.e. it is switched from value four to value five the aforementioned signal conditions in their entirety, so that the logic circuit 86 absorbs the address digits V * * 1 and W. The register 6 * is thus omitted for the address of the memory! ld ·· Md-IV in which the 0.9 <ache multiplicand, ie the value 03 22 is stored »In the ~ min following t3A-t3B cycles, this value is

109808/1587

BAD ORIGINAL Docket GE 866 077

a total of four times in the described manner to the content of the accumulator register 2 ⁽ added. With each such iteration the content of the registers 12 * and 13 * is changed by one is displayed, the AND circuit 106 remains closed and this register is advanced at clock time t3B via the AND circuit 105 in the downward direction. However, the signal state | 3 = 1, ~ ψ ~ * 0 is displayed for register 13 *, so that the AND circuit 107 is closed and the AND circuit 108 is opened. The last-mentioned AND circuit therefore sends a signal via the OR circuit 101 to the control line 75 at the clock time t3B, which signal contains the content of the b-register β 13 * increased by 1. The process just described is repeated once during each iteration, so that after the fourth iteration the a-register 12 'has the value one and the h-register 13 * has the value ten.

When the b register 13 'changes to ten, the logic circuits connected to this register deliver a new signal state which is as follows: b * * 0, b ¹ »1, ρ * 0, ρ a 1. These signals reach the logic circuit 85, which it combines with the signals a · «1, a '« 0, <* * 0, oe * 1 generated unchanged for the a register 12' to form the address numbers V «0 and W '* 1. At time t3A of the fifth t3A-t3B cycle in the second clock cycle, the address of the memory field Md-I 'is therefore transferred to the memory 3'. The next clock signal t3B therefore causes the addition of the 1-fold multiplicand to the content of the

109808/1587

BAD ORIG'NAL

Docket GE 866 077

Us

Accumulator register 2 ', which has thus increased to the value 165349. The same clock pulse reaches the control line 74 via the AND circuit 105 opened by the flip-flop 85, whereby the content 1 of the a-register 12 'su zero is reduced. If both registers IZ 'and 13 * are now at zero, the signal on line 37 decays so that AND circuits 94 and 95 in clock generator 90 are blocked and AND circuit 96 prepares for the passage of the next tA signal will. This signal, which triggers the clock signal t4A, switches the counter 53 · further to the switching state t4. The subsequently generated clock signal t4A ab transfers the product field address from the register 4 'via the gate circuit 42' to the memory ^ ¹ . The next clock signal t4B causes the ^{partial product located in the accumulator register 2 1 to be} transmitted via the gate circuit 9 'to the memory 3', where it is stored ^{in the addressed product field Pt 1.}

The actual multiplication operation is thus ended. The product field contains the value 16 53 49 QOt The clock generator 90 ends its second Circulation and is then switched off. This shutdown can take place, for example, at the beginning of the third cycle if, during the attempt, the next multiplier byte to be taken from the memory 3 *, one End of field mark is determined.

The exemplary embodiments shown can be modified to the extent that al · da · 0, cache of the multiplicand is not stored, but by a Wiping the output of the memory · 3 or 3 'and the input of the

108808/1587 ^{BAD 0RIG |} nal

Docket GE 866 077

Adding unit 1 or 1 'arranged digit shift circuit generated will. In this case, the 0.1-fold multiplicand is selected by that with the help of one of the address numbers V, W or V, W the simple Multiplicand is addressed while the second address digit is used for Control of the digit shift circuit is used, which is a shift of the 1-fold multiplicand taken from the memory by one digit to the right and thus 0.1-fold the multiplicand forms.

Another possible modification is that the multiplication device according to the invention uses the known principle of the optional use of the single or double multiplicand for the respective addition or subtraction iteration to be carried out. To do this, x. B. with the exclusive execution of additions (working method of execution »in games according to Fig. 1) in addition to the 1-, 0.1- and, l _r l -fold multiplicands also the 2.0-, 2.2- and to form 0.2 fold multiplicands. The selection of these multiples can be done in a way that is similar to that in connection with the. 1 and 4A, 4B is essentially analogous to the selection explained. If the 0.1, 0.2 and / or 2-fold «of the multiplicand is not formed in the aforementioned form by position shifting or doubling circuits located between the memory and the adder, three addresses can share in register 6 can be used to select the various multiplicand memory fields. Another possible modification can ultimately also consist in the fact that the various multiplicand multiples are not in different fields.

109808/1687

Docket GE 866 077 B ^AD

- 99

J ¹ I

that of a memory, but in a separate register each. The selection signals V ₁ W or V, W are used in such a case to control gate circuits, which are arranged between .dea outputs of these registers and the input of the adder 3 bgw, 3 '.

108808/1587

BAD 0R1G5NAL Docket GE 866 077

Claims (11)

PATENT CLAIMS 1. Multiplication device with means for the formation and accumulation of multiplicand multiples under control of stored multiplier digits, characterized in that the multiplier digits are supplied in pairs to a control register circuit (12, 13), which depends on whether the high-digit, the low-digit or neither of the two Digits is zero, the choice under the 0 ,. 1-, 1- or 1, making the multiplicand controls «which is then added to a partial product, as indicated by the non-zero or smaller of the digits. 2. Multiplication device according to claim 1 * characterized in that that for each digit of a multiplier digit pair · a counting register (12, 13) is provided, the content of which is changed by one with each iteration and is continuously updated by logic circuits (30, 31) the presence of the value NuU is scanned, and that the content is zero, or content-non-NuU display signals (a ·, b «) as binary Address numbers for the selection of the various multiples to serve. 3. Multiplication device according to claim 1 and 2, characterized in that that the multiplicand locations are adjacent fields (Md-I, Md-II, Md-ΠΙ) of the main memory (3) of a data processing 109808/1587 New document ^ i ν **** ·> ^ <"^ ** - ⁴ Docket GE 866 077 _{ßAD or1} gMAL St. are processing machine and that the content-zero or content-non-zero display ^{properties (a 1} , b ¹ ) of the multiplier digit counting register (12, 13) are used to distinguish these fields. 4. Multiplication device according to claim 1 and 2, characterized in that the multiplicand storage locations are separate registers from which, depending on the content-zero or content-non-zero display signals (a ¹ * b), the multiplier digit count ! register (12, 13) is selected for each iteration and coupled to the adder via gate circuits. 5. Multiplication device according to Claims 1 and 2, thereby marked that only the 1-fold multiplicand and its 1 * 1-fold are stored in special memory fields or registers and the 0, guard multiplicand by shifting the simple multiplicand is obtained when it is transmitted to the adder. 6. Multiplication device according to one or more of the claims 1 to 5 with means for optionally repeated addition or subtraction of the multiplicand or its multiple, depending on whether the multiplier to be processed is less than six or greater than five, characterized in that in addition to the 0.1 ×, 1.0 × and 1.1 times the multiplicand also its 0.9 times bot is available and that the content of the multiplier is digit 109808/1587 BAD ORIGINAL Docket GE 866 077 - 3ΤΓ - Counting register (12 ·, 13 ·) derived "content>5" or "content ^ 6" display signals (<* or oc or /J or /?) Together with the content zero or non-zero Signals (a * or a 'or b' or b ·) are fed to a logic circuit (85) which, if a "content>5" is present, display signals (<*. A ¹ ) for the higher-digit (a) a pairs of multiplier digits to be processed in parallel and, if there is a content-zero display signal β (a ¹ ) for the higher-digit digit together with a "content>5" display signal (ß · b ¹ ) for the lower-digit digit (b), the adder-subtracter ( 1 ') supplies a subtraction control signal and, if the two content non-zero display signals (a' · b ') and the display signal ¹ V unequal / 3 "(ot · φ +« · fi) are present, a selection control signal combination generated for 0.9 times the multiplicand. 7. multiplication device according to claim 6, characterized in that that the multiplier digit counting register (\ 2 \ 13 ') depending on the presence of "content < 6" or "content>5" - display signals (<*, ρ or ei, / 9) either according to the real or the complementary The value of the entered multiplier digits can be switched further during successive iterations. 8. Multiplication device according to speeches 6 and 7th thereby marked «that depending on the existence of a content 109808/1587 bath Docket GC 866 077 > 5 display signal (ß or «) for the one multiplier digit counting control tor (13 · or 12 ') the content of · the next higher multiplier digit (a or b) receiving counting register (e.g. 12 'or 13' in the next Circulation) is increased by one in each case via logic circuits (102 or 85 and 100) before the start of the iteration sequence controlled by this number. 9. Multiplication device according to claims 6 to 8, characterized in that dal} the logic circuit (85) the relationship ADD a (a ¹ · «Γ + a ⁷ - b ¹ · / Γ) and
SUB ■ aW + a "b'P * ADD met, wherein ADD and SUB operation control signals for the adder-subtracter (P) are. 10. Multiplication device according to claims 6 to 9 »characterized in that the logic circuit (85 ^{) generates two selection control signals (V 1} , W) which in combination as address signals for the selection of the four multiplicand multiples 0.1; 1.0; 1.1 and 0.9 serve a. 11. Multiplication device according to claim 2 or 7, characterized in that that by a clock (50 or 90) the advancement of the multiplier digit-ZlMr egistcr (12, 13 or 12 ·, 13 ') and thus also the «vtl. Change of selection control signals (V, W or V *. W) takes place at the same time in which the Addierbzw. Adding and subtracting unit (1 or 1 ') because selected multiple 109808/1587 bad original Docket GE 866 07? Multiples of the multiplier added to the previous partial product or subtracted from this, so that if the multiplicand digit pair in the * counting registers is another iteration requires, this can be carried out with a changed multiplicand multiple without loss of cycle time. 10 9 8 08/1587 BATH Docket GE 866 077 HO _t Blank page