GB1173799A - Computer Arrangement for Controlling a Plurality of Co-operating Means - Google Patents
Computer Arrangement for Controlling a Plurality of Co-operating MeansInfo
- Publication number
- GB1173799A GB1173799A GB04150/67A GB1415067A GB1173799A GB 1173799 A GB1173799 A GB 1173799A GB 04150/67 A GB04150/67 A GB 04150/67A GB 1415067 A GB1415067 A GB 1415067A GB 1173799 A GB1173799 A GB 1173799A
- Authority
- GB
- United Kingdom
- Prior art keywords
- work
- processor
- functions
- store
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Quality & Reliability (AREA)
- Software Systems (AREA)
- Exchange Systems With Centralized Control (AREA)
- Telephonic Communication Services (AREA)
- Hard Magnetic Materials (AREA)
- Compounds Of Iron (AREA)
Abstract
1,173,799. Automatic exchange systems. TELEFONAKTIEBOLAGET L. M. ERICSSON. 28 March, 1967 [25 March, 1966], No. 14150/67. Heading H4K. A telephone exchange TA is controlled by a central processor comprising data processing units D1-D3 (each having duplicate sections A and B with processors CE and interchangeable programme stores IM) and call data stores DM (each having duplicate sections A and B;) the interface between the processor and the exchange having transfer units FE1-FE3 (with duplicate sections A and B); and a switching field KN being provided so that throughout the processing of any work function the particular combinations of units D, DM and FE can be connected to one another as appropriate to the task in hand. Supervision of the exchange line circuits LU, the link circuits SNK, tone senders TS, code senders and receivers KS and KM, incoming and outgoing junctions FIR and FUR, and of the network SLGV, is made direct over 16 wire links from the processing units D1-D3 which signal address registers FA so as to gate access circuits LT, VT, RT1 and RT2 appropriately to results registers FR. Control of the exchange by the processor is effected by instructing the address registers FA to give access to buffer stores SMR to which commands are sent by way of the results registers. Address registers FA are followed by decoders AO. The processing units pursue different interests; D1 may be concerned with line and network scanning; D2 being concerned with network control and control and part supervision of the relay sets, senders and junctions, by way of RMR, RT1 and RT2; while D3 may be concerned with the reception and sending of digits. The processors CE (Fig. 2, not shown), each comprise a logic unit (LE), a number of registers (RA, RB, RC) and a control circuit (SE) having a microprogramme governing processor functions in accordance with instructions from the programme store IM. The function of the control circuit (SE) when instructed to determine the state of a subscriber's line and compare the result with the last determined state as recorded in a call store DM is described with reference to Fig. 3, not shown. The co-operation of the processing units D1-D3 with call stores DM1-DM3 is shown in an abbreviated fashion in Fig. 4a for the detection of a calling subscriber, his connection to a code receiver and his connection to the local called party. For convenience the transfer units FE1-FE3 are shown as having specialized functions but it is stated that their functions are in fact common. The processing steps are indicated by numbered data routes. (1), (2) and (3); D1, FE1 and DM1, co-operate in detecting the calling condition and in selecting an idle code receiver and a path between that and the calling subscriber. (4); Transfers the path switching data to DM2 which (5), with D2 and FE2 establishes the connection of the code receiver. (6); Transfers the identity of the code receiver to DM3 from DM2, and (7), DM3, D3 and FE3 detect and store the dialled codes sent by the calling subscriber. (8) and (9); Transfer the wanted party identity from DM3 to DM2 and by cooperation of DM3, D2 and FE2 disconnect the code receiver. (10 and (11); D1 and DM1 select paths between both subscribers and a free link circuit and pass the data to DM2 so that (12), D2 and FE2 can establish the connections in the exchange. A similar scheme is set out (Fig. 4b, not shown) for the establishment of an outgoing call. To provide a queuing system for the demands made by the processor units D1-D3 on the call stores DM1-DM3 and transfer units FE1-FE3 each call store and transfer unit has a separate address register and result register for each processing unit, the corresponding pairs of address and results registers being served cyclically (Fig. 5, not shown). While each processing unit D1-D3 has a complete programme capacity the extent to which the capacity of each unit is drawn from is limited by a so-called indicating memory (I.F.) (in the processing unit or call store), which determines what parts of the programme are the concern of each particular unit and in what sequence they are to be taken. A unit supervisory programme store (KM0) establishes the priority of the task being undertaken and a system supervisory programme store (SM0) regulates the allocation of time to priority levels of work and organizes avoiding action when fault or processor overload conditions occur. With processor overload the system supervision sheds in essential work functions by cancelling corresponding sections of the indicating memory (I.F.) and, if this is not sufficient, essential functions can be transferred from the indicating memory (I.F.) of the overloaded processor to the memory of a processor having spare capacity (Figs. 10 and 13, not shown). The work functions of the processing system have three levels of priority A, B and C, and the supervisory programme store (KM0) allots time for work in each level deciding, on the completion of each programmed action whether work shall continue at that level or be superceded by work at an inferior level, it being arranged that work of A priority is always undertaken at the start of successive 10 m.s. periods. An interrupted programme section of B or C priority is stored pending a resumption of work at that level. The number of consecutive interruptions of B level work functions to take up A level functions is counted to see the extent to which C level functions are being overlooked entirely. Moreover, the number of consecutive preruptions of C level work which leave C level work pending is counted. Counts of either kind beyond a predetermined number are an indication of overload conditions. If a processor CE fails the work functions are passed to another processor by transfer of the work list contained in the indicating memory (I.F.) (Fig. 11, not shown). If a call store DM fails its contents are transferred to a standby call store (Fig. 12, not shown).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE3972/66A SE313849B (en) | 1966-03-25 | 1966-03-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1173799A true GB1173799A (en) | 1969-12-10 |
Family
ID=20263248
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB04150/67A Expired GB1173799A (en) | 1966-03-25 | 1967-03-28 | Computer Arrangement for Controlling a Plurality of Co-operating Means |
Country Status (11)
Country | Link |
---|---|
US (1) | US3503048A (en) |
BE (1) | BE695581A (en) |
BR (1) | BR6787980D0 (en) |
DE (1) | DE1549550C3 (en) |
ES (1) | ES338194A1 (en) |
FI (1) | FI45811B (en) |
FR (1) | FR1515604A (en) |
GB (1) | GB1173799A (en) |
NL (1) | NL158628B (en) |
NO (1) | NO121631B (en) |
SE (1) | SE313849B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109656868A (en) * | 2018-11-19 | 2019-04-19 | 浙江大学宁波理工学院 | A kind of internal storage data transfer method between CPU and GPU |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE755034A (en) * | 1969-08-19 | 1971-02-19 | Siemens Ag | CENTRAL CONTROLLED INFORMATION PROCESSING INSTALLATION PROGRAM BY MEMORY |
US4115866A (en) * | 1972-02-25 | 1978-09-19 | International Standard Electric Corporation | Data processing network for communications switching system |
US4044333A (en) * | 1972-07-26 | 1977-08-23 | Siemens Aktiengesellschaft | Data processing switching system |
BE789828A (en) * | 1972-10-09 | 1973-04-09 | Bell Telephone Mfg | DATA PROCESSING OPERATING SYSTEM. |
GB1411182A (en) * | 1973-01-04 | 1975-10-22 | Standard Telephones Cables Ltd | Data processing |
US3828321A (en) * | 1973-03-15 | 1974-08-06 | Gte Automatic Electric Lab Inc | System for reconfiguring central processor and instruction storage combinations |
US3920977A (en) * | 1973-09-10 | 1975-11-18 | Gte Automatic Electric Lab Inc | Arrangement and method for switching the electronic subsystems of a common control communication switching system without interference to call processing |
US4099241A (en) * | 1973-10-30 | 1978-07-04 | Telefonaktiebolaget L M Ericsson | Apparatus for facilitating a cooperation between an executive computer and a reserve computer |
US3964056A (en) * | 1974-04-08 | 1976-06-15 | International Standard Electric Corporation | System for transferring data between central units and controlled units |
IT1014277B (en) * | 1974-06-03 | 1977-04-20 | Cselt Centro Studi Lab Telecom | CONTROL SYSTEM OF PROCESS COMPUTERS OPERATING IN PARALLEL |
CH608902A5 (en) * | 1975-04-21 | 1979-01-31 | Siemens Ag | |
US4040023A (en) * | 1975-12-22 | 1977-08-02 | Bell Telephone Laboratories, Incorporated | Recorder transfer arrangement maintaining billing data continuity |
GB1572894A (en) * | 1976-03-04 | 1980-08-06 | Post Office | Data processing equipment |
US4070704A (en) * | 1976-05-17 | 1978-01-24 | Honeywell Information Systems Inc. | Automatic reconfiguration apparatus for input/output processor |
NL7608165A (en) * | 1976-07-23 | 1978-01-25 | Philips Nv | DEVICE FOR CONTROLLING INFORMATION FLOWS. |
US4117317A (en) * | 1976-08-09 | 1978-09-26 | Dynage, Incorporated | Programmable controller with hardwired backup connecting terminals and related control system using programmable controller and hardwired backup |
US4099234A (en) * | 1976-11-15 | 1978-07-04 | Honeywell Information Systems Inc. | Input/output processing system utilizing locked processors |
SE414087B (en) * | 1977-02-28 | 1980-07-07 | Ellemtel Utvecklings Ab | DEVICE IN A COMPUTER SYSTEM FOR SENDING SIGNALS FROM A PROCESSOR TO ONE OR MANY OTHER PROCESSORS WHERE PRIORITY SIGNALS ARE SENT DIRECTLY WITHOUT TIME DELAY AND OPRIORATED SIGNALS ORDER ... |
US4358823A (en) * | 1977-03-25 | 1982-11-09 | Trw, Inc. | Double redundant processor |
US4245306A (en) * | 1978-12-21 | 1981-01-13 | Burroughs Corporation | Selection of addressed processor in a multi-processor network |
SE439208B (en) * | 1983-09-30 | 1985-06-03 | Ericsson Telefon Ab L M | PROGRAMMED CONTROL TELECOMMUNICATIONS |
GB2217487B (en) * | 1988-04-13 | 1992-09-23 | Yokogawa Electric Corp | Dual computer system |
NL193573C (en) * | 1989-04-04 | 2000-02-02 | Yokogawa Electric Corp | Duplex computer system. |
WO2002089457A1 (en) * | 2001-04-30 | 2002-11-07 | Octave Communications, Inc. | Audio conferencing system and method |
US20060068870A1 (en) * | 2004-09-13 | 2006-03-30 | Pokertek, Inc. | Electronic card table and method with host console |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3200380A (en) * | 1961-02-16 | 1965-08-10 | Burroughs Corp | Data processing system |
US3363234A (en) * | 1962-08-24 | 1968-01-09 | Sperry Rand Corp | Data processing system |
US3319226A (en) * | 1962-11-30 | 1967-05-09 | Burroughs Corp | Data processor module for a modular data processing system for operation with a time-shared memory in the simultaneous execution of multi-tasks and multi-programs |
US3312947A (en) * | 1963-12-31 | 1967-04-04 | Bell Telephone Labor Inc | Plural memory system with internal memory transfer and duplicated information |
US3374465A (en) * | 1965-03-19 | 1968-03-19 | Hughes Aircraft Co | Multiprocessor system having floating executive control |
US3386082A (en) * | 1965-06-02 | 1968-05-28 | Ibm | Configuration control in multiprocessors |
US3312954A (en) * | 1965-12-08 | 1967-04-04 | Gen Precision Inc | Modular computer building block |
-
1966
- 1966-03-25 SE SE3972/66A patent/SE313849B/xx unknown
-
1967
- 1967-02-23 US US618193A patent/US3503048A/en not_active Expired - Lifetime
- 1967-02-28 NL NL6703232.A patent/NL158628B/en not_active Application Discontinuation
- 1967-03-10 FI FI0730/67A patent/FI45811B/fi active
- 1967-03-15 NO NO167300A patent/NO121631B/no unknown
- 1967-03-16 BE BE695581D patent/BE695581A/xx unknown
- 1967-03-18 ES ES338194A patent/ES338194A1/en not_active Expired
- 1967-03-22 BR BR187980/67A patent/BR6787980D0/en unknown
- 1967-03-23 DE DE1549550A patent/DE1549550C3/en not_active Expired
- 1967-03-24 FR FR100252A patent/FR1515604A/en not_active Expired
- 1967-03-28 GB GB04150/67A patent/GB1173799A/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109656868A (en) * | 2018-11-19 | 2019-04-19 | 浙江大学宁波理工学院 | A kind of internal storage data transfer method between CPU and GPU |
CN109656868B (en) * | 2018-11-19 | 2022-12-06 | 浙江大学宁波理工学院 | Memory data transfer method between CPU and GPU |
Also Published As
Publication number | Publication date |
---|---|
ES338194A1 (en) | 1968-06-16 |
SE313849B (en) | 1969-08-25 |
DE1549550C3 (en) | 1974-01-31 |
NL158628B (en) | 1978-11-15 |
NO121631B (en) | 1971-03-22 |
NL6703232A (en) | 1967-09-26 |
US3503048A (en) | 1970-03-24 |
BE695581A (en) | 1967-09-01 |
BR6787980D0 (en) | 1973-09-11 |
DE1549550A1 (en) | 1971-03-18 |
DE1549550B2 (en) | 1973-06-14 |
FI45811B (en) | 1972-05-31 |
FR1515604A (en) | 1968-03-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PLNP | Patent lapsed through nonpayment of renewal fees |