ES338194A1 - Arrangement in computers for controlling a plant consisting of a plurality of cooperating means - Google Patents

Abstract

A telephone exchange TA is controlled by a central processor comprising data processing units D1-D3 (each having duplicate sections A and B with processors CE and interchangeable programme stores IM) and call data stores DM (each having duplicate sections A and B) the interface between the processor and the exchange having transfer units FE1-FE3 (with duplicate sections A and B) and a switching field KN being provided so that throughout the processing of any work function the particular combinations of units D, DM and FE can be connected to one another as appropriate to the task in hand. Supervision of the exchange line circuits LU, the link circuits SNK, tone senders TS, code senders and receivers KS and KM, incoming and outgoing junctions FIR and FUR, and of the network SLGV, is made direct over 16 wire links from the processing units D1-D3 which signal address registers FA so as to gate access circuits LT, VT, RT1 and RT2 appropriately to results registers FR. Control of the exchange by the processor is effected by instructing the address registers FA to give access to buffer stores SMR to which commands are sent by way of the results registers. Address registers FA are followed by decoders AO. The processing units pursue different interests D1 may be concerned with line and network scanning D2 being concerned with network control and control and part supervision of the relay sets, senders and junctions, by way of RMR, RT1 and RT2 while D3 may be concerned with the reception and sending of digits. The processors CE (Fig. 2, not shown), each comprise a logic unit (LE), a number of registers (RA, RB, RC) and a control circuit (SE) having a microprogramme governing processor functions in accordance with instructions from the programme store IM. The function of the control circuit (SE) when instructed to determine the state of a subscriber's line and compare the result with the last determined state as recorded in a call store DM is described with reference to Fig. 3, not shown. The co-operation of the processing units D1-D3 with call stores DM1-DM3 is shown in an abbreviated fashion in Fig. 4a for the detection of a calling subscriber, his connection to a code receiver and his connection to the local called party. For convenience the transfer units FE1-FE3 are shown as having specialized functions but it is stated that their functions are in fact common. The processing steps are indicated by numbered data routes. (1), (2) and (3) D1, FE1 and DM1, co-operate in detecting the calling condition and in selecting an idle code receiver and a path between that and the calling subscriber. (4) Transfers the path switching data to DM2 which (5), with D2 and FE2 establishes the connection of the code receiver. (6) Transfers the identity of the code receiver to DM3 from DM2, and (7), DM3, D3 and FE3 detect and store the dialled codes sent by the calling subscriber. (8) and (9) Transfer the wanted party identity from DM3 to DM2 and by cooperation of DM3, D2 and FE2 disconnect the code receiver. (10 and (11) D1 and DM1 select paths between both subscribers and a free link circuit and pass the data to DM2 so that (12), D2 and FE2 can establish the connections in the exchange. A similar scheme is set out (Fig. 4b, not shown) for the establishment of an outgoing call. To provide a queuing system for the demands made by the processor units D1-D3 on the call stores DM1-DM3 and transfer units FE1-FE3 each call store and transfer unit has a separate address register and result register for each processing unit, the corresponding pairs of address and results registers being served cyclically (Fig. 5, not shown). While each processing unit D1-D3 has a complete programme capacity the extent to which the capacity of each unit is drawn from is limited by a so-called indicating memory (I.F.) (in the processing unit or call store), which determines what parts of the programme are the concern of each particular unit and in what sequence they are to be taken. A unit supervisory programme store (KM0) establishes the priority of the task being undertaken and a system supervisory programme store (SM0) regulates the allocation of time to priority levels of work and organizes avoiding action when fault or processor overload conditions occur. With processor overload the system supervision sheds in essential work functions by cancelling corresponding sections of the indicating memory (I.F.) and, if this is not sufficient, essential functions can be transferred from the indicating memory (I.F.) of the overloaded processor to the memory of a processor having spare capacity (Figs. 10 and 13, not shown). The work functions of the processing system have three levels of priority A, B and C, and the supervisory programme store (KM0) allots time for work in each level deciding, on the completion of each programmed action whether work shall continue at that level or be superceded by work at an inferior level, it being arranged that work of A priority is always undertaken at the start of successive 10 m.s. periods. An interrupted programme section of B or C priority is stored pending a resumption of work at that level. The number of consecutive interruptions of B level work functions to take up A level functions is counted to see the extent to which C level functions are being overlooked entirely. Moreover, the number of consecutive preruptions of C level work which leave C level work pending is counted. Counts of either kind beyond a predetermined number are an indication of overload conditions. If a processor CE fails the work functions are passed to another processor by transfer of the work list contained in the indicating memory (I.F.) (Fig. 11, not shown). If a call store DM fails its contents are transferred to a standby call store (Fig. 12, not shown).