GB1167528A - Radix Conversion Circuits - Google Patents

Abstract

1,167,528. Radix converters. INTERNATIONAL BUSINESS MACHINES CORP. 12 Dec., 1966 [30 Dec., 1965], No. 55459/66. Heading G4A. A radix converter with means for selecting the target radix gates the input number to an arithmetic circuit under the control of the selecting means to generate a sum representing the units digit of the output number, the difference of the input number and this sum being used in a similar way to obtain the next output digit, and so on. The conversion algorithm is applicable to any initial radix C and final radix m which satisfy for some non-negative integers n and P, and parameters for a number of possible cases are listed in the Specification, but two embodiments described in detail are as follows. In the first embodiment, binary data can be converted to binary-coded decimal or binarycoded radix 12 form, using most of the equipment in common for the two cases. The bits of the binary input are read from memory in turn, low order first, and each used to pass the units digit of the output radix equivalent of the bit, in 8-4-2-1 parallel form to an accumulator for addition without carry to the sum of such units digits derived from the previous bits of the binary input, this sum being temporarily stored in four latches. The final result in these latches, being the units digit of the output radix equivalent of the input binary number, is now subtracted from the input binary number by feeding both together, serially-by-bit, low order first, to the accumulator which is now operating as a subtractor with a borrow feed-back via a one-bit delay. The serial-by-bit accumulator output is placed in the memory and then divided by the output radix 10 or 12. This is done by a one-bit shift followed by a division by 5 using subtraction in the case of radix 10, and a two-bit shift followed by a division by 3 using subtraction in the case of radix 12. The shift is done by reading from memory high order first, and back into memory via a suitable delay, and the subtractive division is done (reading from memory low order first) using the accumulator with serial-by-bit inputs and outputs, a borrow output of the accumulator being fed back to the input via a one-bit delay and the accumulator result output, besides being stored in the memory, being fed to the accumulator input via a one or two-bit delay (for the divide by 3 and 5 cases respectively). The division result is used to obtain the next output digit in the same way, and so on. In the second embodiment, binary-coded ternary data can be converted to selectively binary-coded decimal or binary-coded radix 12 form. This embodiment is similar to the first except that the accumulator inputs and outputs are weighted 6-3-2-1 rather than 8-4-2-1, ternary digits are always transferred parallel-by-bit, the shifts are 1 and 0 positions for output radices 12 and 10 respectively and the following subtractive divisions are therefore by 4 and 10 respectively. Pence in binary-coded-form may be converted to pounds, shillings and pence using two conversions, from base 2 to base 12, then base 12 to base 20.