GB1113314A - Delay circuit using an ultrasonic delay line - Google Patents
Delay circuit using an ultrasonic delay lineInfo
- Publication number
- GB1113314A GB1113314A GB48095/65A GB4809565A GB1113314A GB 1113314 A GB1113314 A GB 1113314A GB 48095/65 A GB48095/65 A GB 48095/65A GB 4809565 A GB4809565 A GB 4809565A GB 1113314 A GB1113314 A GB 1113314A
- Authority
- GB
- United Kingdom
- Prior art keywords
- delay
- line
- signal
- signals
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C21/00—Digital stores in which the information circulates continuously
- G11C21/02—Digital stores in which the information circulates continuously using electromechanical delay lines, e.g. using a mercury tank
- G11C21/026—Digital stores in which the information circulates continuously using electromechanical delay lines, e.g. using a mercury tank using magnetostriction transducers, e.g. nickel delay line
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
- Ultra Sonic Daignosis Equipment (AREA)
- Pulse Circuits (AREA)
Abstract
1,113,314. Delay system. SONY CORPORATION. 12 Nov., 1965 [14 Nov., 1964], No. 48095/65. Heading H4R. A number of register input signals, X1 to X4, of a computer are delayed by feeding them in time division multiplex on to a single ultrasonic delay line 9 and feeding the output signal of the line to a demultiplexer to derive the individual delayed signal. A counter 5 is fed by a pulse generator 3 so that the outputs Cl to C4 are each enabled in turn once in each bit period of the register signals of the lines X1 to X4. The gates A1 to A4 are thus opened in turn to feed the incoming signals through " OR " gate 7 and drive circuit 8 to feed the line 9 in time division multiplex. The output from the line, after a two bit delay, is fed via reading amplifier 10 to the gates A1<SP>1</SP> to A4<SP>1</SP>, which are also fed with the signals from the counter 5 so that they open in turn to feed the delayed signals from inputs X1 to X4 into the respective flip-flop FF1 to FF4 which is set by a signal pulse and reset by a clock pulse signal at the bit rate of the information. The reset of a flip-flop FF1 to FF4 is arranged to set the respective flip-flop FF1<SP>1</SP> to FF4<SP>1</SP> which is arranged to be reset by the following clock pulse so that the signal on lines XI<SP>1</SP> to X4<SP>1</SP> reproduces that on lines X1 to X4, respectively, after a delay of 3 bit periods.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6449464 | 1964-11-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1113314A true GB1113314A (en) | 1968-05-15 |
Family
ID=13259798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB48095/65A Expired GB1113314A (en) | 1964-11-14 | 1965-11-12 | Delay circuit using an ultrasonic delay line |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE1296178C2 (en) |
| FR (1) | FR1454203A (en) |
| GB (1) | GB1113314A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB748438A (en) * | 1953-11-30 | 1956-05-02 | Marconi Wireless Telegraph Co | Improvements in or relating to ultrasonic delay devices |
| DE1136734B (en) * | 1956-11-08 | 1962-09-20 | Gen Electric | Arrangement for exactly matching delay of two or more pulse series |
-
1965
- 1965-11-12 DE DE1965S0100507 patent/DE1296178C2/en not_active Expired
- 1965-11-12 FR FR38236A patent/FR1454203A/en not_active Expired
- 1965-11-12 GB GB48095/65A patent/GB1113314A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR1454203A (en) | 1966-07-22 |
| DE1296178C2 (en) | 1979-12-13 |
| DE1296178B (en) | 1969-05-29 |
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