GB1097401A - Improvements in or relating to computer circuit demonstrating devices - Google Patents

Improvements in or relating to computer circuit demonstrating devices

Info

Publication number
GB1097401A
GB1097401A GB969764A GB969764A GB1097401A GB 1097401 A GB1097401 A GB 1097401A GB 969764 A GB969764 A GB 969764A GB 969764 A GB969764 A GB 969764A GB 1097401 A GB1097401 A GB 1097401A
Authority
GB
United Kingdom
Prior art keywords
socket
terminating
circuits
gate circuits
transistor gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB969764A
Inventor
Richard Joseph Mark Zgorski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LAN ELECTRONICS Ltd
Original Assignee
LAN ELECTRONICS Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LAN ELECTRONICS Ltd filed Critical LAN ELECTRONICS Ltd
Priority to GB969764A priority Critical patent/GB1097401A/en
Publication of GB1097401A publication Critical patent/GB1097401A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09BEDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS
    • G09B23/00Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes
    • G09B23/06Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics
    • G09B23/18Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism
    • G09B23/183Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits
    • G09B23/186Models for scientific, medical, or mathematical purposes, e.g. full-sized devices for demonstration purposes for physics for electricity or magnetism for circuits for digital electronics; for computers, e.g. microprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Algebra (AREA)
  • Computational Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Analysis (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Business, Economics & Management (AREA)
  • Educational Administration (AREA)
  • Educational Technology (AREA)
  • Theoretical Computer Science (AREA)
  • Instructional Devices (AREA)

Abstract

1,097,401. Educational appliances. LANELECTRONICS Ltd. March 8, 1965 [March 6, 1964], No. 9697/64. Heading G5G. An apparatus for demonstrating computer circuits comprises a set of transistor gate circuits T having input and output terminal sockets 3, 4, respectively, for co-operation with detachable cords (not shown) by which selected transistor gate circuits can be interconnected to stimulate digital computer circuits, in combination with a dial switch 8 adapted to generate trains of pulses. In the embodiment shown there are fifteen transistor gate circuits T, mounted on the underside of a panel 1 in five columns and three rows with the input and output terminal sockets 3, 4 mounted on the upper surface of the panel. In each gate circuit the transisitor emitter is connected to a common grounded rail terminating in a socket 5. The collector is connected through a lead resistance to a common negative rail terminating in a socket 6 and the base through a lead resistance to a common positive bias rail terminating in a socket 7. The dial 8 is arranged to transmit impulses by opening a pair of normally-closed contacts, any number of times from one to ten, and connected between the negative rail and one end of a voltage divider the other end of which is connected to ground. The voltage divider comprises two resistors in series the junction between them being connected to a number of terminal sockets 9 which may be connected by said cords to the input terminals 3. The apparatus is further provided with a set of lamps 10, one for each column, having one end connected to a socket 5 and the other terminating in a socket 11 which may be connected to the output of a selected gate. A set of pushbuttons 12 are provided for resetting the gate circuits. Each column is arranged so that with suitable components interconnecting appropriate sockets a digital store may be formed and also be capable of providing a buffer between the digital store and one of the indicating lamps.
GB969764A 1964-03-06 1964-03-06 Improvements in or relating to computer circuit demonstrating devices Expired GB1097401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB969764A GB1097401A (en) 1964-03-06 1964-03-06 Improvements in or relating to computer circuit demonstrating devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB969764A GB1097401A (en) 1964-03-06 1964-03-06 Improvements in or relating to computer circuit demonstrating devices

Publications (1)

Publication Number Publication Date
GB1097401A true GB1097401A (en) 1968-01-03

Family

ID=9877022

Family Applications (1)

Application Number Title Priority Date Filing Date
GB969764A Expired GB1097401A (en) 1964-03-06 1964-03-06 Improvements in or relating to computer circuit demonstrating devices

Country Status (1)

Country Link
GB (1) GB1097401A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728534A (en) * 1971-02-10 1973-04-17 Philips Corp Constructable logic system
CN104599569A (en) * 2014-12-25 2015-05-06 惠州学院 Demonstrating experiment device for NAND gate circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728534A (en) * 1971-02-10 1973-04-17 Philips Corp Constructable logic system
CN104599569A (en) * 2014-12-25 2015-05-06 惠州学院 Demonstrating experiment device for NAND gate circuit

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